Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria

• US 6,370,637 B1
• Filed: 08/05/1999
• Issued: 04/09/2002
• Est. Priority Date: 08/05/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Oberman, Stuart F., Weber, Frederick D., Juffa, Norbert, Meier, Stephan G.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/370,789
• Time in Patent Office: 978 Days
• Field of Search: 709/104, 712/215, 712/222
• US Class Current: 712/215
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point unit'"'"'s pipeline (e.g., during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessor'"'"'s execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.

Claims

1. A method for allocating a plurality of instructions to a plurality of execution pipelines, the method comprising:

receiving the plurality of instructions, wherein one or more of the plurality of instructions are multi-pipeline executable, wherein the remaining instructions are single-pipeline executable, wherein the multi-pipeline executable instructions are capable of being executed by more than one type of execution pipeline, and wherein the single-pipeline executable instructions are executable by only one type of execution pipeline;

allocating each single-pipeline executable instruction to one of the plurality of execution pipelines according to instruction type; and

allocating each multi-pipeline executable instruction to one of the plurality of execution pipelines according to a set of criteria, wherein the set of criteria includes determining whether at least one other multi-pipeline executable instruction is present in the plurality of instructions.

2. The method as recited in claim 1, wherein the set of criteria further includes determining whether at least one other single-pipeline executable instruction must be executed by a particular pipeline that executes instructions that on average occur less frequently than instructions that must be executed by the other execution pipelines.

3. The method as recited in claim 2, wherein the particular pipeline is a store pipeline.

4. The method as recited in claim 1, wherein the criteria further includes allocating the plurality of instructions so that any execution pipelines configured to perform store operations receive on average as many multi-pipeline executable instructions as the remaining execution pipelines combined.

5. The method as recited in claim 1, wherein the criteria further includes determining if there are two or more multi-pipeline executable instructions in the plurality of instructions, and, if so, refraining from allocating the multi-pipeline executable instructions to a particular one of the execution pipelines that executes single-pipeline executable instructions that on average occur more frequently than single-pipeline executable instructions that must be executed by the other execution pipelines.

6. The method as recited in claim 5, wherein the particular pipeline is a store pipe.

7. The method as recited in claim 1, wherein the criteria further includes determining if there are two or more multi-pipeline executable instructions in the plurality of instructions, and, if so, then allocating each multi-pipeline executable instructions to a different execution pipeline to the extent possible.

8. The method as recited in claim 1, wherein the criteria includes allocating instructions to the execution pipelines in substantially inverse proportion to the average number of non-multi-pipeline executable instructions received by each execution pipeline.

9. The method as recited in claim 1, wherein the criteria includes allocating slightly more multi-pipeline executable instructions to the execution pipelines configured to execute multiplication instructions relative to the number of multi-pipe executable instructions allocated to execution pipelines configured to execute addition instructions.

10. A method for allocating a plurality of instructions to a plurality of execution pipelines, wherein the plurality of execution pipelines comprises at least one addition pipeline, at least one multiplication pipeline, and at least one store pipeline, the method comprising:

receiving the plurality of instructions, wherein one or more of the plurality of instructions are junk ops; and

allocating each of the plurality of instructions that are not junk ops according to instruction type; and

allocating each of the plurality of instructions that are junk ops to maximize compliance with at least the following criteria;

(i) the one or more store pipelines receive on average as many junk ops as the one or more addition pipelines and one or more multiplication pipelines combined.

11. The method as recited in claim 10, wherein the criteria further includes:

(ii) if there are more stores than store pipelines, then no junk ops are sent to store pipelines.

12. The method as recited in claim 11, wherein the criteria further includes:

(iii) no execution pipelines receive more than one junk ops per clock cycle.

13. The method as recited in claim 12, wherein the criteria further includes:

(iv) the one or more addition pipelines receive more junk ops on average than the multiplication pipelines.

14. A microprocessor comprising:

an instruction cache configured to store integer instructions and floating point instructions; and

a floating point unit configured to receive the floating point instructions from the instruction cache, wherein the floating point unit comprises;

a plurality of execution pipelines; and

a rename unit configured to allocate the floating point instructions received by the floating point unit to the execution pipelines, wherein the floating point instructions include single pipeline executable instructions that are executable by a particular type of execution pipeline and multi-pipeline executable instructions that are executable by more than one particular type of execution pipeline, wherein the rename unit is configured to allocate multi-pipeline executable instructions substantially in accordance with at least the following criteria;

(i) the execution pipelines configured to execute store instructions receive on average as many multi-pipeline executable instructions as the execution pipelines configured to execute add and multiply instructions combined.

15. The method as recited in claim 14, wherein a first number of execution pipelines are configured to execute store instructions, wherein the criteria further include:

(ii) if there are more store instructions in a particular clock cycle than the first number, then no multi-pipeline executable instructions are sent to the execution pipelines configured to execute store instructions.

16. The method as recited in claim 14, wherein the criteria further include:

(iii) no execution pipelines receive more than one multi-pipeline executable instruction per clock cycle.

17. The method as recited in claim 14, wherein a first number of execution pipelines are configured to execute store instructions, wherein a second number of execution pipelines are configured to execute add instructions, wherein a third number of execution pipelines are configured to execute multiply instructions, wherein the criteria further include:

(iv) the pipelines configured to execute add instructions receive more multi-pipeline executable instructions on average than the pipelines configured to execute multiply instructions.

18. A computer system comprising:

a main memory;

a communications device; and

a microprocessor coupled to the main memory and the communications device, wherein the microprocessor comprises;

an instruction cache configured to store floating point instructions and integer instructions; and

a floating point unit coupled to receive the floating point instructions from the instruction cache, wherein the floating point unit comprises;

a plurality of execution pipelines; and

a rename unit configured to allocate the floating point instructions received by the floating point unit to the execution pipelines, wherein the floating point instructions include single pipeline executable instructions that are executable by a particular type of execution pipeline and multi-pipeline executable instructions that are executable by more than one particular type of execution pipeline, wherein the rename unit is configured to allocate multi-pipeline executable instructions substantially in accordance with at least the following criteria;

(i) the execution pipelines configured to execute store instructions receive on average as many multi-pipeline executable instructions as the execution pipelines configured to execute add and multiply instructions combined.

19. The system as recited in claim 18, wherein the criteria further include:

(iii) no execution pipelines receive more than one multi-pipeline executable instruction per clock cycle.

20. A computer software program embodied on a computer-readable media, wherein the program comprises a plurality of instructions, wherein the plurality of instructions are configured to:

allocate a plurality of instructions to a plurality of execution pipelines, wherein the plurality of execution pipelines comprises at least one addition pipeline, at least one multiplication pipeline, and at least one store pipeline, wherein the instructions are configured to allocate each of the plurality of instructions that are non-multi-pipeline executable according to instruction type and each of the plurality of instructions that are multi-pipeline executable according to at least the following criteria;

(i) the one or more store pipelines receive on average as many multi-pipeline executable instructions as the one or more addition pipelines and one or more multiplication pipelines combined; and

(ii) if there are more stores than the number of store pipelines, no multi-pipeline executable instructions are sent to the one or more store pipelines.