Data hierarchy layout correction and verification method and apparatus

• US 6,370,679 B1
• Filed: 09/16/1998
• Issued: 04/09/2002
• Est. Priority Date: 09/17/1997
• Status: Expired due to Term

• Current Assignee: Synopsys Merger Holdings LLC (Synopsys Incorporated)
• Original Assignee: Numerical Technologies Inc. (Synopsys Incorporated)
• Inventors: Wang, Yao-Ting, Chang, Fang-Cheng, Pati, Yagyensh C.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/154,415
• Time in Patent Office: 1,301 Days
• Field of Search: 716/5, 716/19-21, 430/30, 430/5
• US Class Current: 716/53
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.

Claims

1. A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising:

providing the integrated circuit layout design as a first input;

providing a particular set of correction criteria as a second input;

analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria;

generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and

providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises;

generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.

2. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the first program data is provided on a computer readable media.

3. The method of generating proximity corrections for an integrated circuit layout of claim 2 wherein the computer readable media comprises a hard disk drive.

4. The method of generating proximity corrections for an integrated circuit layout of claim 2 wherein the computer readable media comprises a server.

5. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the integrated circuit layout is described by a GDS-II data file.

6. The method of generating proximity corrections for an integrated circuit layout of claim 5 wherein the first program data is described by a GDS-II data file.

7. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.

8. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.

9. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the particular set of correction criteria comprises a criteria for specifically identifying transistor gates in the layout.

10. The method of generating proximity corrections for an integrated circuit layout of claim 9 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.

11. The method of generating proximity corrections for an integrated circuit layout of claim 1 further comprising combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.

12. The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.

13. The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

14. The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising:

providing a set of layout accuracy parameters;

comparing the first corrected layout to the design accuracy parameters;

providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

15. The method of generating proximity corrections for an integrated circuit layout of claim 14 further comprising:

providing the second corrected layout to a design rule checker;

operating the design rule checker; and

determining whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

16. The method of generating proximity corrections for an integrated circuit layout of claim 14, wherein comparing the first corrected layout to the design accuracy parameters further comprises:

providing the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce;

providing the actual image of the exposure that was designed for the integrated circuit; and

measuring the difference between the simulated image and the actual image.

17. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.

18. The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

19. A program storage device readable by a machine storing a program of instructions executable by the machine to perform method steps for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising:

providing the integrated circuit layout as a first input;

providing a particular set of correction criteria as a second input;

analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria;

generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction rules; and

providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises;

generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.

20. The program storage device of claim 19 wherein the first program data is provided on a computer readable media.

21. The program storage device of claim 20 wherein the computer readable media comprises a hard disk drive.

22. The program storage device of claim 20 wherein the computer readable media comprises a server.

23. The program storage device of claim 19 wherein the integrated circuit layout is described by a GDS-II data file.

24. The program storage device of claim 23 wherein the first program data is described by a GDS-II data file.

25. The program storage device of claim 19 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.

26. The program storage device of claim 19 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.

27. The program storage device of claim 19 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.

28. The program storage device of claim 27 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.

29. The program storage device of claim 19, the method further comprising combining the first program data with the data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.

30. The program storage device of claim 29, the method further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.

31. The program storage device of claim 29, the method further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

32. The program storage device of claim 29, the method further comprising:

providing a set of layout accuracy parameters;

comparing the first corrected layout to the design accuracy parameters;

providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

33. The program storage device of claim 32, the method further comprising:

providing the second corrected layout to a design rule checker;

operating the design rule checker; and

determining whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

34. The program storage device of claim 32, wherein comparing the first corrected layout to the design accuracy parameters further comprises:

providing the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce;

providing the actual image of the exposure that was designed for the integrated circuit; and

measuring the difference between the simulated image and the actual image.

35. The program storage device of claim 19 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.

36. The program storage device of claim 19 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

37. An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the apparatus comprising:

a first input that receives the integrated circuit layout;

a second input that receives a particular set of correction criteria;

a resource that analyzes the integrated circuit layout and identifies features that meet the particular set of correction criteria;

a resource that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and

a resource that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the resource for providing the first program data further;

generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.

38. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the first program data is provided on a computer readable media.

39. The apparatus for generating proximity corrections for an integrated circuit layout of claim 38 wherein the computer readable media comprises a hard disk drive.

40. The apparatus for generating proximity corrections for an integrated circuit layout of claim 38 wherein the computer readable media comprises a server.

41. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the integrated circuit layout is described by a GDS-II data file.

42. The apparatus for generating proximity corrections for an integrated circuit layout of claim 41 wherein the first program data is described by a GDS-II data file.

43. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.

44. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.

45. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.

46. The apparatus for generating proximity corrections for an integrated circuit layout of claim 45 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.

47. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 further comprising a resource that combines the first program data with the data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.

48. The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising a resource that flattens the second program data to produce a third program data, and a resource that utilizes the third program data to produce an optically corrected lithographic mask.

49. The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising a design rule checker that receives the second program data and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

50. The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising:

a third input that receives a set of layout accuracy parameters;

a resource that compares the first corrected layout to the design accuracy parameters;

a resource that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

a resource that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

51. The apparatus for generating proximity corrections for an integrated circuit layout of claim 50 further comprising a design rule checker that receives the second corrected mask and determines whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

52. The apparatus for generating proximity corrections for an integrated circuit layout of claim 50, wherein comparing the first corrected layout to the design accuracy parameters further comprises:

a resource that provides the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce;

a resource that provides the actual image of the exposure that was designed for the integrated circuit; and

a resource that measures the difference between the simulated image and the actual image.

53. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.

54. The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

55. A computer program product, comprising:

a computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the computer readable program code comprising;

computer readable program code that reads the integrated circuit layout as a first input;

computer readable program code that reads a particular set of correction criteria as a second input;

computer readable program code that analyzes the integrated circuit layout to identify features that meet the particular set of correction criteria;

computer readable program code that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and

computer readable program code that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the computer readable program code that provides a first program data computer further comprises;

computer readable program code that generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.

56. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the first program data is provided on a computer readable media.

57. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 56 wherein the computer readable media comprises a hard disk drive.

58. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 56 wherein the computer readable media comprises a server.

59. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the integrated circuit layout is described by a GDS-II data file.

60. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 59 wherein the first program data is described by a GDS-II data file.

61. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.

62. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.

63. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.

64. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 63 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.

65. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 further comprising computer readable program code that combines the first program data with data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.

66. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising a computer readable program code that flattens the second program data to produce a third program data, and a computer readable program code that utilizes the third program data to produce a corrected lithographic mask.

67. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising a computer readable program code that receives the second program data as a third input and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

68. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising:

a computer readable program code that receives a set of layout accuracy parameters as a third input;

a computer readable program code that compares the first corrected layout to the design accuracy parameters;

a computer readable program code that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

a computer readable program code that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

69. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 68 further comprising a computer readable program code that receives the second corrected mask as a fourth input and determines whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

70. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 68, wherein the computer readable program code that compares the corrected layout to the design accuracy parameters further comprises:

a computer readable program code that receives the second program and produces a simulated image of the exposure that the corrected layout would produce;

a computer readable program code that provides the actual image of the exposure that was designed for the integrated circuit; and

a computer readable program code that measures the difference between the simulated image and the actual image.

71. The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

72. A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the method comprising:

providing the integrated circuit layout as a first input;

providing a particular set of correction criteria as a second input;

compiling the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the hierarchical tree structure in response to the particular set of correction criteria;

linking the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell'"'"'s child cells and interaction between the cell'"'"'s primitive geometry and each of the cell'"'"'s child cells; and

providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.

73. The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein for each cell in the hierarchical tree structure the sum of the delta plane of the cell and the delta planes of the cell'"'"'s child cells comprises a correction plane of the cell wherein the correction plane for the cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

74. The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the first program data is provided on a computer readable media.

75. The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the integrated circuit layout is described by a GDS-II data file.

76. The method of generating proximity corrections for an integrated circuit layout of claim 75 wherein the first program data is described by a GDS-II data file.

77. The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.

78. The method of generating proximity corrections for an integrated circuit layout of claim 72 further comprising combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.

79. The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.

80. The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

81. The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising:

providing a set of layout accuracy parameters;

comparing the first corrected layout to the design accuracy parameters;

providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

82. The method of generating proximity corrections for an integrated circuit layout of claim 81 further comprising providing the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

83. An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the apparatus comprising:

a first input that receives the integrated circuit layout;

a second input that receives a particular set of correction criteria;

a resource that compiles the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the tree structure in response to the particular set of correction criteria;

a resource that links the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell'"'"'s child cells and interaction between the cell'"'"'s primitive geometry and each of the cell'"'"'s child cells; and

a resource that provides a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.

84. The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein for each cell in the hierarchical tree structure the sum of the delta plane of the cell and the delta planes of the cell'"'"'s child cells comprises a correction plane of the cell wherein the correction plane for the cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.

85. The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the first program data is provided on a computer readable media.

86. The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the integrated circuit layout is described by a GDS-II data file.

87. The apparatus for generating proximity corrections for an integrated circuit layout of claim 86 wherein the first program data is described by a GDS-II data file.

88. The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.

89. The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 further comprising a resource that combines the first program data with data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.

90. The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising a resource that flattens the second program data to produce a third program data, and a resource that utilizes the third program data to produce an optically corrected lithographic mask.

91. The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising a design rule checker that receives the second program data and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

92. The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising:

a third input that receives a set of layout accuracy parameters;

a resource that compares the first corrected layout to the design accuracy parameters;

a resource that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

a resource that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

93. The apparatus for generating proximity corrections for an integrated circuit layout of claim 92 further comprising a resource that provides the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.

94. A method for laying out a layer in an integrated circuit, comprising:

defining a layout using a hierarchical structure including a plurality of layout cells combined according to the hierarchical structure to generate said layout;

traversing the plurality of layout cells in the hierarchical structure to compile correction data for the layout, the correction data defining changes in the layout; and

linking the correction data to the hierarchical structure, while substantially preserving the plurality of layout cells in the hierarchical structure, wherein the layout cells include at least one of a primitive geometry and references to child cells in the plurality of layout cells, wherein said correction data comprises delta planes for respective cells in the plurality of layout cells, such that the delta plane of a particular cell in the plurality of layout cells defines changes to correct for interaction between the child cells identified by references in the particular cell, and for interaction between the primitive geometry in the particular cell and said referenced child cells; and

providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical structure of the layout.

95. The method of claim 94, wherein said traversing includes analyzing the plurality of layout cells to identify features of the layout suitable for proximity correction, and generating proximity correction data for such features.

96. The method of claim 94, further comprising combining the first program data with the plurality of layout cells in the hierarchical structure to produce a second program data that describes a first corrected layout.

97. The method of claim 96, further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.

98. The method of claim 96, further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.

99. The method of claim 96, further comprising:

providing a set of layout accuracy parameters;

comparing the first corrected layout to the design accuracy parameters;

providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and

applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.

100. The method of claim 99, further comprising providing the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.