Method of manufacturing an image-sensor integrated circuit package without resin flash on lead frame and with increased wire bondability

• US 6,372,551 B1
• Filed: 05/12/2000
• Issued: 04/16/2002
• Est. Priority Date: 05/12/2000
• Status: Expired due to Fees

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Huang, Chien Ping
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/571,117
• Time in Patent Office: 704 Days
• Field of Search: 438/106, 438/108, 438/118, 438/121, 438/124, 438/125, 438/126, 438/128, 438/51, 438/55, 438/122, 438/127
• US Class Current: 438/124
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

An integrated circuit (Integrated Circuit) packaging method is proposed, which can be used to pack an Integrated Circuit chip of an optically-sensitive type, such as an image-sensor Integrated Circuit chip, and which can help prevent resin flash on lead frame and help increase wire bondability. The proposed Integrated Circuit packaging method can help prevent resin flash on the die-pad portion and the inner end of the finger portion of the lead frame. This benefit allows the die attachment on the die-pad portion of the lead frame to be more reliable than the prior art. Moreover, the proposed Integrated Circuit packaging method allows lead frame to come into direct thermal contact with heat block during wire-bonding process, so that it allows an increased level of bondability to the bonding wires, making the Integrated Circuit package more assured in quality and more reliable to use than the prior art.

Claims

1. An Integrated Circuit packaging method, comprising the steps of:

(1) preparing a lead frame having a die-pad portion and a finger portion;

(2) preparing an encapsulating mold including a top inserted mold and a bottom inserted mold, wherein the top inserted mold is formed with a first side-wall cavity structure while the bottom inserted mold is formed with a second side-wall cavity structure;

(3) clamping the lead frame between the top inserted mold and the bottom inserted mold in such a manner that the die-pad portion and the inner end of the finger portion of the lead frame would be substantially airtightly covered between the top inserted mold and the bottom inserted mold;

(4) filling a molding material into the first side-wall cavity structure in the top inserted mold to thereby form a top side-wall structure having a centrally-hollowed portion, and also into the second side-wall cavity structure in the bottom inserted mold to thereby form a bottom side-wall structure having a centrally-hollowed portion;

(5) removing the encapsulating mold;

(6) performing a die-attachment process to attach at least one Integrated Circuit chip on the die-pad portion of the lead frame;

(7) performing a wire-bonding process to electrically couple the Integrated Circuit chip to the inner end of the finger portion of the lead frame, and in which step the bottom side-wall structure is placed on a heat block shaped in such a manner that allows the die-pad portion and the inner end of the finger portion to come in direct thermal contact with the heat block through the centrally-hollowed portion of the bottom side-wall structure;

(8) Removing the heat block; and

(9) performing a lidding process to cover a lid onto the opening of the top side-wall structure.

2. The Integrated Circuit packaging method of claim 1, wherein the Integrated Circuit chip is an image-sensor Integrated Circuit chip.

3. The Integrated Circuit packaging method of claim 1, wherein a base encapsulating block is further formed in the centrally-hollowed portion of the bottom side-wall structure.

4. The Integrated Circuit packaging method of claim 3, wherein the base encapsulating block is formed by filling epoxy into the centrally-hollowed portion of the bottom side-wall structure.

5. The Integrated Circuit packaging method of claim 3, wherein the base encapsulating block is formed by filling silicone into the centrally-hollowed portion of the bottom side-wall structure.

6. An Integrated Circuit packaging method, comprising the steps of:

(1) preparing a lead frame having a die-pad portion and a finger portion;

(2) preparing an encapsulating mold including a top inserted mold and a bottom inserted mold, wherein the top inserted mold is formed with a first side-wall cavity structure while the bottom inserted mold is formed with a second side-wall cavity structure;

(3) clamping the lead frame between the top inserted mold and the bottom inserted mold in such a manner that the die-pad portion and the inner end of the finger portion of the lead frame would be substantially airtightly covered between the top inserted mold and the bottom inserted mold;

(4) filling a molding material into the first side-wall cavity structure in the top inserted mold to thereby form a top side-wall structure having a centrally-hollowed portion, and also into the second side-wall cavity structure in the bottom inserted mold to thereby form a bottom side-wall structure having a centrally-hollowed portion;

(5) removing the encapsulating mold;

(6) performing a first die-attachment process to attach a first Integrated Circuit chip on the back side of the die-pad portion of the lead frame; and

then

performing a first wire-bonding process to electrically couple the first Integrated Circuit chip to the back side of the inner end of the finger portion of the lead frame, and in which step the bottom side-wall structure is placed on a first heat block shaped in such a manner that allows the front side of the die-pad portion and the inner end of the finger portion to come in direct thermal contact with the first heat block through the centrally-hollowed portion of the top side-wall structure;

(7) performing a second die-attachment process to attach a second Integrated Circuit chip on the front side of the die-pad portion of the lead frame; and

then

performing a second wire-bonding process to electrically couple the second Integrated Circuit chip to the front side of the inner end of the finger portion of the lead frame, and in which step the bottom side-wall structure is placed on a second heat block shaped in such a manner that allows the back side of the die-pad portion and the inner end of the finger portion to come in direct thermal contact with the second heat block through the centrally-hollowed portion of the bottom side-wall structure;

(8) forming a base encapsulating block in the centrally-hollowed portion of the bottom side-wall structure after the second heat block is removed; and

(9) performing a lidding process to cover a lid onto the opening of the top side-wall structure.

7. The Integrated Circuit packaging method of claim 6, wherein the second Integrated Circuit chip is an image-sensor Integrated Circuit chip.

8. The Integrated Circuit packaging method of claim 6, wherein in said step (8), the base encapsulating block is formed by filling epoxy into the centrally-hollowed portion of the bottom side-wall structure.

9. The Integrated Circuit packaging method of claim 6, wherein in said step (8), the base encapsulating block is formed by filling silicone into the centrally-hollowed portion of the bottom side-wall structure.