Electrooptic device, driving substrate for electrooptic device, and method of manufacturing the device and substrate

• US 6,372,558 B1
• Filed: 08/18/1999
• Issued: 04/16/2002
• Est. Priority Date: 08/18/1998
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sato, Yuichi, Yamoto, Hisayoshi, Yagi, Hajime, Yamanaka, Hideo
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US09/376,840
• Time in Patent Office: 972 Days
• Field of Search: 438/149, 438/29, 438/30, 438/150, 438/155, 349/41, 349/42, 349/43, 349/47, 349/84, 349/139
• US Class Current: 438/149
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/105 single crystal Si
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/2205 from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/6678 on sapphire substrates, e.g. SOS transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel

Abstract

The present invention provides an active matrix substrate having a built-in high-performance driver, in which a single crystal silicon thin film having high electron/hole mobility is uniformly deposited at a relatively low temperature, and an electrooptic device such as a thin film semiconductor device for display including the active matrix substrate. The single crystal silicon thin film is deposited by hetero epitaxial growth by a catalytic CVD method or the like using a crystalline sapphire thin film formed on the substrate as a seed so that the single crystal silicon layer obtained is used for top gate type MOSTFTs of the electrooptic device such as a LED or the like in which a display region and a peripheral driving circuit region are integrated.

Claims

1. A method of manufacturing an electrooptic device comprising a first substrate comprising a display region in which pixel electrodes are arranged, and a peripheral driving circuit region arranged in the periphery of the display region, a second substrate, and an optical material interposed between a first substrate and a second substrate, the method comprising the steps of:

forming step portions in one side of the first substrate;

depositing a single crystal semiconductor layer on the first substrate including the step portions by graphoepitaxial growth by a catalytic CVD or high-density plasma CVD method using the step portions as seeds;

forming channel, source and drain regions in the single crystal semiconductor layer after growth of the single crystal semiconductor layer; and

forming gate portions of the channel regions to form top gate type first thin film transistors which constitute at least a portion of the peripheral driving circuit region, wherein the first thin film transistors are respectively provided in the step portions of the first substrate.

2. A method of manufacturing an electrooptic device according to claim 1, wherein the step portions are formed into recessed portions having a sectional shape in which a side is at a right angle with a bottom or inclined toward a lower end, so as to be used as the seeds for graphoepitaxial growth of the single crystal semiconductor layer.

3. A method of manufacturing an electrooptic device according to claim 1, wherein the step portions are formed in the first substrate by dry etching, and the single crystal semiconductor layer is formed at 200 to 800°

C.

4. A method of manufacturing an electrooptic device according to claim 1, wherein the single crystal semiconductor layer is a single crystal silicon layer, which is formed on the first substrate by the catalytic CVD method comprising bringing a gas containing silicon hydride as a main component into contact with a heated catalyst.

5. A method of manufacturing an electrooptic device according to claim 4, wherein silane is used as the silicon hydride, and at least one material selected from the group consisting of tungsten, tungsten containing thorium oxide, molybdenum, platinum, palladium, silicon, alumina, ceramics with metals adhered thereto, and silicon carbide.

6. A method of manufacturing an electrooptic device according to claim 1, wherein a diffusion barrier layer is formed on the first substrate, and the single crystal semiconductor layer is formed on the diffusion barrier layer.

7. A method of manufacturing an electrooptic device according to claim 1, wherein in deposition of the single crystal semiconductor layer, III-group or V-group impurity element is mixed to control the type and/or concentration of the impurity of the single crystal semiconductor layer.

8. A method of manufacturing an electrooptic device according to claim 1, wherein the first thin film transistors are respectively provided in recessed portions of the first substrate, which are formed by the step portions.

9. A method of manufacturing an electrooptic device according to claim 1, wherein each of the step portions is formed along at least one side of an element region comprising the channel, source and drain regions of each of the first thin film transistors.

10. A method of manufacturing an electrooptic device according to claim 1, wherein after growth of the single crystal semiconductor layer, an upper gate portion comprising a gate insulating film and a gate electrode is formed on the single crystal semiconductor layer so that a III-group or V-group element is introduced into the single crystal silicon layer by using the upper gate portion as a mask to form the channel, source and drain regions.

11. A method of manufacturing an electrooptic device according to claim 1, wherein besides the first thin film transistors, a thin film transistor comprising a channel region made of a polycrystalline or amorphous silicon layer, or at least one element selected from the group consisting of a diode, a resistor, a capacitor, and an inductor is provided in the peripheral driving circuit region.

12. A method of manufacturing an electrooptic device according to claim 1, wherein switching elements are provided on the first substrate, for switching each of the pixel electrodes in the display region.

13. A method of manufacturing an electrooptic device according to claim 12, wherein the first thin film transistors are top gate type thin film transistors, and the switching elements comprise second thin film transistors.

14. A method of manufacturing an electrooptic device according to claim 13, wherein the second thin film transistors are bottom gate type or dual gate type, and lower gate electrodes comprising a heat resistant material are provided below channel regions of the second thin film transistors, and gate insulating films are formed on the lower gate electrodes to form lower gate portions, followed by the step of forming the step portions, and the step of forming the first thin film transistors.

15. A method of manufacturing an electrooptic device according to claim 14, wherein the second thin film transistors are the dual gate type thin film transistors, and upper gate electrodes of the second thin film transistors are made of a material common to the gate portions of the first thin film transistors.

16. A method of manufacturing an electrooptic device according to claim 14, wherein after the single crystal semiconductor layer is formed on the lower gate portions, a III-group or V-group element is introduced into the single crystal semiconductor layer to form source and drain regions, followed by activation.

17. A method of manufacturing an electrooptic device according to claim 16, wherein after the single crystal semiconductor layer is formed, source and drain regions of each of the first and second thin film transistors are formed by ion implantation of the III-group or V-group element using a resist mask, followed by activation.

18. A method of manufacturing an electrooptic device according to claim 13, wherein the second thin film transistors are a top gate type, and after the single crystal semiconductor layer is formed, source and drain regions of each of the first and second thin film transistors are formed by ion implantation of the III-group or V-group element using a resist mask, and a gate portion of each of the first and second thin film transistors, which comprises a gate insulating film and a gate electrode, is then formed after activation.

19. A method of manufacturing an electrooptic device according to claim 13, wherein the second thin film transistors are top gate type, and after the single crystal semiconductor layer is formed, a gate insulating film and a gate electrode made of heat resistant material are formed to form a gate portion in each of the first and second thin film transistors, and source and drain regions are formed by ion implantation of an impurity element using the gate portion in each of the first and second thin film transistors as a mask, followed by activation.

20. A method of manufacturing an electrooptic device according to claim 13, wherein at least some of the thin film transistors in the peripheral driving circuit region and the display region have a LDD (lightly doped drain) structure.

21. A method of manufacturing an electrooptic device according to claim 20, wherein a resist mask used for forming the LDD structure is left, and another resist mask is formed to cover the remaining resist mask and used for forming the source and drain regions by ion implantation.

22. A method of manufacturing an electrooptic device according to claim 1, wherein the first substrate is a glass substrate or a heat-resistant organic substrate.

23. A method of manufacturing an electrooptic device according to claim 1, wherein when the pixel electrodes are reflective electrodes, irregularity is formed in a resin film so that the pixel electrodes are transparent electrodes, a surface of the resin film is flattened by a transparent planarizing film so that the pixel electrodes are provided on the planarizing film.

24. A method of manufacturing an electrooptic device according to claim 1, wherein the first thin film transistors are respectively provided in projected portions of the first substrate, which are formed by the step portions.

25. A method of manufacturing a driving substrate for an electrooptic device comprising a substrate on which a display region in which pixel electrodes are arranged, and a peripheral driving circuit region arranged in the periphery of the display region are provided, the method comprising the steps of:

forming step portions in one side of the substrate;

depositing a single crystal semiconductor layer on the substrate including the step portions by graphoepitaxial growth by a catalytic CVD or high-density plasma CVD method using the step -portions as seeds; and

forming channel, source and drain regions in the single crystal semiconductor layer after growth of the single crystal semiconductor layer; and

forming gate portions of the channel regions to form top gate type first thin film transistors which constitute at least a portion of the peripheral driving circuit region, wherein the first thin film transistors are respectively provided in the step portions of the substrate.

26. A method of manufacturing an electrooptic device comprising a first substrate comprising a display region in which pixel electrodes are arranged, and a peripheral driving circuit region arranged in the periphery of the display region, a second substrate, and an optical material interposed between the first and second substrates, the method comprising the steps of:

forming a material layer having high lattice matching with a single crystal semiconductor on a side of the first substrate;

depositing a single crystal semiconductor layer on the first substrate including the material layer by hetero-epitaxial growth by a catalytic CVD or high-density plasma CVD using the material layer as a seed; and

forming active elements by predetermined processing of the single crystal semiconductor layer.

27. A method of manufacturing a driving substrate for an electrooptic device comprising a substrate comprising a display region in which pixel electrodes are arranged, and a peripheral driving circuit region arranged in the periphery of the display region, the method comprising the steps of:

forming a material layer having high lattice matching with a single crystal semiconductor on a side of the substrate;

depositing a single crystal semiconductor layer on the substrate including the material layer by hetero-epitaxial growth by a catalytic CVD or high-density plasma CVD using the material layer as a seed; and

forming at least active elements by predetermined processing of the single crystal semiconductor layer.