Self-aligned trench capacitor capping process for high density DRAM cells

• US 6,372,573 B2
• Filed: 10/26/1999
• Issued: 04/16/2002
• Est. Priority Date: 10/26/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc., Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Porth, Bruce W., Inoue, Hirofumi, Buschner, Paul C., Levy, Max G., Aoki, Masami, Fisch, Emily E., Nastasi, Victor R.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/426,754
• Publication Number:
  US 20010039088A1
• Time in Patent Office: 903 Days
• Field of Search: 438/243-249, 438/386-392
• US Class Current: 438/248
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Claims

1. A process for planarizing a trench capping layer used to isolate shallow capacitate trenches comprising:

etching a surface of a polysilicon layer to recess the surface over a buried trench with a collar;

depositing a silicon nitride trench capping film on said polysilicon layer and a recessed portion over said buried trench;

patterning an area above said trench to create a cavity, wherein said cavity is located in a part of the recessed portion;

oxidizing areas of said trench exposed by said patterning step;

filling said cavity and said recessed portion;

removing excess fill;

removing said silicon nitride trench capping film located on said polysilicon layer, and leaving silicon nitride trench capping film covered with the fill.

2. The process of claim 1, wherein said removing said excess fill step includes chemical etching.

3. The process of claim 1, wherein said removing said excess fill step includes chemical-mechanical polishing.

4. The process of claim 1, including the following steps prior to said etching step:

depositing a pad through a silicon nitride deposition over said buried trench;

pattering said pad to open an area over said buried trench.

5. The process of claim 1, further comprising:

forming an oxide film on said recessed portion prior to depositing said silicon nitride trench capping film.

6. A trench capacitor in a semiconductor memory formed by a process comprising:

etching a surface of a polysilicon layer to recess the surface over a buried trench with a collar;

depositing a silicon nitride trench capping film on said polysilicon layer and a recessed portion over said buried trench;

pattering an area above said buried trench to create a cavity;

oxidizing areas of said buried trench exposed by said pattering step;

filling cavity and said recessed portion;

removing excess fill;

removing said silicon nitride trench capping film located on said polysilicon layer.

7. The trench capacitor according to claim 6, further comprising the following steps prior to said etching step:

depositing a pad through a silicon nitride deposition over said buried trench;

pattering said pad to open an area over said buried trench.

8. The process according to claim 6, further comprising:

forming an oxide film on said recessed portion prior to depositing said silicon nitride trench capping film.

9. A process for planarizing a trench capping layer used to isolate shallow capacitate trenches comprising:

forming a buried trench filled with a polysilicon layer in a semiconductor substrate;

etching a surface of the polysilicon layer to recess the surface over said buried trench with a collar;

depositing a silicon nitride trench capping film on a recessed portion over said buried trench;

pattering an area above said buried trench to create a cavity;

filling said cavity and said recessed portion;

removing excess fill; and

removing said silicon nitride trench capping film located on said polysilicon layer.

10. The process according to claim 9, including a step of oxidizing said recessed portion prior to said depositing step of said silicon nitride trench capping film.

11. The process according to claim 9, including a step of oxidizing a surface of said cavity prior to said filling step.

12. The process according to claim 9, further comprising:

forming an oxide film on said recessed portion prior to depositing said silicon nitride trench capping film.

13. A process for planarizing a trench capping layer used to isolated shallow capacitate trenches comprising:

forming a pad on a semiconductor substrate;

forming an opening in said pad;

forming a buried trench filled with a polysilicon layer in a semiconductor substrate through the opening, said buried trench having a collar;

etching a surface of the polysilicon layer through the opening to recess the surface over said buried trench;

depositing a silicon nitride trench capping film on said pad and recessed portion over said buried trench;

patterning an area above said buried trench to create a cavity;

filling said cavity and said recessed portion by a dielectric material;

removing excess fill; and

removing said pad on said semiconductor substrate and said silicon nitride trench capping film located on said pad.

14. The process according to claim 13, further comprising:

forming an oxide film on said recessed portion to depositing said silicon nitride trench capping film.