Core cell structure and corresponding process for NAND type performance flash memory device

• US 6,372,577 B1
• Filed: 11/18/1999
• Issued: 04/16/2002
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Fang, Hao
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/443,647
• Time in Patent Office: 880 Days
• Field of Search: 438/257-267
• US Class Current: 438/258
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A method of forming a NAND-type flash memory device (200 ) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.

Claims

1. A method of forming a NAND-type flash memory device, comprising the steps of:

forming a floating gate region over a tunnel oxide layer on a core region of a substrate;

forming an insulating layer over the floating gate region;

performing a periphery dual oxide process, thereby forming an oxide region having a first thickness in a high voltage periphery region and an oxide region having a second thickness in both a low voltage periphery region and in a select gate transistor region in the core region, wherein the first thickness is greater than the second thickness;

forming a conductive layer over a surface of the device; and

patterning the conductive layer to form a gate over the oxide region in the low voltage periphery region and in the select gate transistor region, respectively, to thereby form a low voltage periphery transistor and a select gate transistor, and form a gate over the oxide region in the high voltage periphery region and thereby form a high voltage periphery transistor and form a control gate over the insulating layer to thereby form a stacked gate flash memory cell in the core region.

2. The method of claim 1, wherein forming a floating gate region over a tunnel oxide layer on a core region of the substrate comprises the steps of:

forming the tunnel oxide layer over the substrate;

forming a conductive layer over the tunnel oxide layer; and

patterning the conductive layer and tunnel oxide layer to form a layered structure in the core region of the substrate, wherein the conductive layer comprises the floating gate region.

3. The method of claim 1, wherein forming the insulating layer comprises the steps of:

depositing a first oxide layer;

depositing a nitride layer over the first oxide layer; and

depositing a second oxide layer over the nitride layer.

4. The method of claim 1, wherein performing a peripheral dual oxide process comprises the steps of:

forming an oxide layer over a surface of the device;

forming and patterning a mask over the oxide layer, thereby forming a plurality of openings in the mask that define a plurality of regions wherein an oxide region having the second thickness will be formed;

etching the oxide layer, thereby removing the oxide layer in regions defined by the openings in the mask;

removing the mask; and

forming another oxide layer over the surface of the device, wherein a region previously covered by the mask has the first thickness and the plurality of regions previously etched have the second thickness.

5. The method of claim 1, wherein the step of forming the conductive layer comprises the steps of:

depositing a polycrystalline silicon layer;

doping the polycrystalline silicon layer with impurity ions; and

depositing a tungsten silicide layer over the polycrystalline silicon layer.

6. The method of claim 1, further comprising the step of performing a channel stop implant in the select gate transistor region.

7. The method of claim 6, wherein the channel stop implant step uses a mask used to form the floating gate region, thereby providing isolation between one or more bit lines.

8. The method of claim 1, further comprising a threshold voltage adjust implant during the dual oxide process.

9. A method of claim 1, wherein patterning the conductive layer comprises the steps of forming a second gate mask, performing a second gate etch and a self-aligned etch, thereby forming the low voltage and high voltage periphery transistors and the select gate transistor and forming a plurality of stacked gate structures that share the conductive layer to thereby form a word line.