Fine pitch bumping with improved device standoff and bump volume

• US 6,372,622 B1
• Filed: 10/26/1999
• Issued: 04/16/2002
• Est. Priority Date: 10/26/1999
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tan, Qing, Beddingfield, Stanley Craig, Mitchell, Douglas G.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US09/426,982
• Time in Patent Office: 903 Days
• Field of Search: 438/612-614, 228/180.22
• US Class Current: 438/612
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11902 Multiple masking steps
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09436 : Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/09563 : Metal filled via
• CPC Class Codes: H05K 2203/043 : Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
• CPC Class Codes: H05K 2203/054 : Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 3/243 : characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3473 : Plating of solder
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).

Claims

1. A method for forming a bump structure, comprising:

providing a semiconductor device having a bond pad;

forming a first masking layer overlying the bond pad;

patterning the first masking layer to form a first opening overlying at least a portion of the bond pad;

forming a stud at least within the first opening;

forming a second masking layer overlying the first masking layer;

patterning the second masking layer to form a second opening overlying at least a portion of the first opening;

forming a first solder bump at least within the second opening; and

removing the first masking layer and the second masking layer.

2. The method of claim 1, wherein the first masking layer has a thickness in a range of approximately 5 to 50 microns.

3. The method of claim 2, wherein the thickness of the first masking layer is in a range of approximately 10 to 20 microns.

4. The method of claim 1, wherein the first opening is a circular opening.

5. The method of claim 1, wherein the second masking layer has a thickness in a range of approximately 20 to 60 microns.

6. The method of claim 1, wherein the second opening is a rectangular opening.

7. The method of claim 1, wherein the first opening is centered within the second opening.

8. The method of claim 1, wherein forming the first solder bump within the second opening comprises electroplating solder on the stud.

9. The method of claim 1, further comprising removing the first masking layer and the second masking layer after forming the first solder bump.

10. The method of claim 9, further comprising reflowing the first solder bump to form a reflowed solder bump.

11. The method of claim 9, further comprising using the first solder bump to attach the semiconductor device to a substrate.

12. The method of claim 11, wherein the semiconductor device is spaced at least approximately 50 microns apart from the substrate.

13. The method of claim 1, further comprising forming a second solder bump spaced apart from the first solder bump, wherein the first and second solder bumps have a pitch of at most approximately 200 microns.

14. The method of claim 1, wherein the second opening is larger than the first opening.

15. The method of claim 1, wherein the second masking layer is thicker than the first masking layer.

16. The method of claim 1, further comprising forming a first layer overlying the semiconductor device and a portion of the bond pad.

17. The method of claim 16, wherein the first layer includes a barrier layer.

18. The method of claim 16, wherein the first layer includes an adhesion layer.

19. The method of claim 16, wherein forming the stud comprises electroplating copper on the first layer to form a plated copper stud, wherein the first layer includes a seed layer.

20. The method of claim 16, further comprising removing portions of the first layer overlying the semiconductor device.

21. The method of claim 20, further comprising reflowing the first solder bump to form a reflowed solder bump.

22. The method of claim 16, wherein the semiconductor device further comprises a passivation layer overlying the first layer and having an opening that exposes a portion of the first layer overlying the bond pad.

23. The method of claim 1, wherein forming the stud is performed after patterning the second masking layer.