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Edge stress reduction by noncoincident layers

  • US 6,373,088 B2
  • Filed: 06/10/1998
  • Issued: 04/16/2002
  • Est. Priority Date: 06/16/1997
  • Status: Expired due to Term
First Claim
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1. An integrated circuit structure, comprising:

  • a. a substrate having a top surface;

    b. a bottom conductor that is elongate with a substantially rectangular cross-section that presents a longitudinal center axis, two opposed sidewalls spaced apart a certain distance, a bottom wall and a top wall, the bottom wall being arranged adjacent the top surface of the substrate;

    c. a top conductor that is elongate with a substantially rectangular cross-section that presents a longitudinal center axis, two opposed sidewalls, a bottom wall and a top wall, the bottom wall of the top conductor being arranged over the top wall of the bottom conductor, the longitudinal axis of the top conductor being arranged substantially aligned with the longitudinal axis of the bottom conductor, and the sidewalls of the top conductor being spaced apart a distance less than the certain distance between the sidewalls of the bottom conductor;

    d. the top wall of the bottom conductor and the sidewalls of the top conductor being free of any sidewall spacers; and

    e. the lead width of the top conductor being at least 0.8 times the height of the bottom conductor, and the lead width of the top conductor being within the range of 0.4 to 0.8 times the lead width of the bottom conductor.

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