Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device

• US 6,373,098 B1
• Filed: 05/25/1999
• Issued: 04/16/2002
• Est. Priority Date: 05/25/1999
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun, Kocon, Christopher B., Brush, Linda S.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Hu, Shouxiang
• Application Number:
  US09/318,334
• Time in Patent Office: 1,057 Days
• Field of Search: 257/329, 257/330, 257/331, 257/341, 257/328, 257/339, 257/401, 257/396, 257/622, 428/270, 428/271, 428/212, 428/257, 428/589, 428/588, 428/587, 438/269, 438/273
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An improved trench-gated power device comprises a substrate having an overlying layer of epitaxial material disposed on an upper layer of the substrate, well regions containing source and body regions, a trench gate, and a drain region. The improvement comprises a gate trench having beneficially smooth sidewalls that comprise selectively grown epitaxial material and body regions that are recessed with respect to adjacent source regions. In a process for forming an improved trench-gated power device, a dielectric layer having an upper surface and thickness and width dimensions that substantially correspond to the height and width dimensions of a gate trench is formed on an upper layer of the substrate. A layer of epitaxial material is grown on the upper layer of the substrate and the dielectric layer and planarized to be substantially coplanar with the upper surface of the dielectric layer, which is then removed, thereby forming gate trench sidewalls that comprise selectively grown epitaxial material. The process further comprises lining the trench with a dielectric material and substantially filling the lined trench with a conductive material, thereby forming a trench gate, and forming well, body, and source regions in the planarized epitaxial material.

Claims

1. An improved trench-gated power device comprising a substrate having a layer of epitaxial material comprising uniformly doped well regions overlying an upper layer of said substrate, heavily doped source regions and heavily doped body regions contiguous to one another and disposed in an upper portion of said uniformly doped well regions, a gate trench, and a drain region, said gate trench having a floor and sidewalls that are substantially parallel to one another, said sidewalls comprising epitaxial material and being entirely disposed within said uniformly doped well regions, said well regions extending laterally beneath said trench floor,

wherein the improvement comprises:

said heavily doped body regions having upper contact surfaces that are recessed with respect to upper contact surfaces of said contiguous heavily doped source regions.

2. The device of claim 1 wherein said substrate is of a first conduction type and said layer of epitaxial material on said upper layer is of a second opposite conduction type.

3. The device of claim 2 wherein said first conduction type is N and said second conduction type is P.

4. The device of claim 1 wherein said substrate and said epitaxially grown material on said upper layer are both of a first conduction type.

5. The device of claim 1 wherein said upper layer of said substrate is included within said substrate.

6. The device of claim 1 wherein said upper layer of said substrate comprises epitaxial material.

7. The device of claim 1 wherein said well, source, and body regions are included in said layer of epitaxial material.

8. The device of claim 7 wherein said well regions and said layer of epitaxial material are of opposite conduction types.

9. The device of claim 1 wherein said substrate and said layer of epitaxial material comprise silicon.

10. The device of claim 1 wherein said drain region is disposed in a lower portion of said substrate.

11. The device of claim 1 further comprising an interlevel dielectric layer overlying said gate trench and said source regions, and a metal layer overlying said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions, said upper contact surfaces of said source and body regions being continuous with each other.

12. The device of claim 1 wherein said device comprises a plurality of gate trenches.

13. The device of claim 12 wherein said plurality of gate trenches have an open-cell stripe topology.

14. The device of claim 12 wherein said plurality of gate trenches has a closed-cell cellular topology.

15. The device of claim 1 wherein said device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.

16. The device of claim 1 wherein said sidewalls are formed by removing from said layer of epitaxial material an included layer of dielectric material having thickness and width dimensions substantially corresponding to height and width dimensions of said gate trench.

17. The device of claim 16 wherein said layer of dielectric material is removed from said layer of epitaxial material using a buffered oxide etch (BOE) process.