Method of adding filler into a non-filled underfill system by using a highly filled fillet

• US 6,373,142 B1
• Filed: 11/15/1999
• Issued: 04/16/2002
• Est. Priority Date: 11/15/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Hoang, Lan H.
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/440,492
• Time in Patent Office: 883 Days
• Field of Search: 257/780, 257/781, 257/782, 257/783, 257/787, 257/789, 257/795, 438/644, 438/654, 438/118, 438/127, 438/119
• US Class Current: 257/783
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/743 Apparatus for manufacturing layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention provides a semiconductor chip package with a fillet which contains a high percentage of a filler material by weight and a method of assembly with a semiconductor chip package for adding filler material to a non-filled or low-filled underfill system. The method of assembly produces a chip package where the concentration of filler material within the underfill material between the chip and the package substrate may be varied from location to location within the underfill material. The filler material increases the mechanical rigidity of the underfill material after it has hardened. Thus, using the approach of the present invention, the percentage of filler material may be increased in regions of the underfill material where the mechanical stresses require a greater mechanical rigidity. The present invention may be applicable to increasing the reliability of chip packages where the chip and the package substrate are separated by a gap about 25-50 microns wide.

Claims

1. A semiconductor package, comprising;

a packaging substrate having a top side and an underside;

a semiconductor chip having an active surface with a center, a top surface and a perimeter said active surface of said chip electrically and mechanically bonded to the top side of said substrate;

an underfill material between said chip and said substrate wherein the underfill material contains a percentage of filler material;

a second material on top of the said substrate and around the perimeter of the said chip wherein the second material contains a higher percentage of filler material than the underfill material between said chip and said substrate.

2. The semiconductor package of claim 1 wherein the filler material is alumina or silica.

3. The semiconductor package of claim 1 wherein the second material on top of the said substrate and around the side of the said chip forms a fillet.

4. The semiconductor package of claim 1 wherein the underfill material between said chip and said substrate does not contain filler material.

5. The semiconductor package of claim 1 wherein the underfill material between said chip and said substrate contains up to about 30% by weight of filler material.

6. The semiconductor package of claim 1 wherein the second material on top of said substrate and around the perimeter of said chip contains about 30-85% by weight of filler material.

7. The semiconductor package of claim 6 wherein the second material on top of said substrate and around the perimeter of said chip contains about 60-80% by weight of filler material.

8. The semiconductor package of claim 1 wherein the chip and the substrate are separated by a gap about 25-50 microns wide.

9. The semiconductor package of claim 1 wherein the underfill material is a thermo-set epoxy.

10. The semiconductor package of claim 1 wherein the second material on top of said substrate and around the perimeter of said chip is a thermo-set epoxy.

11. The semiconductor package of claim 1 wherein the underfill material between said chip and said substrate contains a gradient of filler material wherein the gradient of filler material varies between the concentration of filler material around the perimeter of said chip and the concentration of filler material at the center of said chip.

12. The semiconductor package of claim 1 wherein the underfill material between said chip and said substrate contains a gradient of filler material wherein the gradient of filler material varies between the concentration of filler material at the active surface of said chip and the concentration of filler material at the top of said substrate.

13. A method of adding filler to an underfill epoxy for chip packaging comprising:

providing a packaging substrate having a top side and an underside and a semiconductor chip having an active surface with a center, a top surface, and a perimeter;

electrically bonding the active surface of said semiconductor chip to electrical traces on the top side of the said substrate;

dispensing an underfill material between said chip and said substrate wherein the underfill material contains a percentage of filler material;

dispensing a second material on top of the said substrate and around the perimeter of the said chip wherein the second material contains a higher percentage of filler material than the underfill material between said chip and said substrate;

curing said underfill material and said second material.

14. The method of claim 13 wherein the filler material is alumina or silica.

15. The method of claim 13 wherein the second material on top of the said substrate and around the perimeter of said chip forms a fillet.

16. The method of claim 13 wherein the underfill material between said chip and said substrate does not contain filler material.

17. The method of claim 13 wherein the underfill material between said chip and said substrate contains up to about 30% by weight of filler material.

18. The method of claim 13 wherein the second material on top of said substrate and around the perimeter of said chip contains about 30-85% by weight of filler material.

19. The method of claim 18 wherein the second material on top of said substrate and around the perimeter of said chip contains about 60-80% by weight of filler material.

20. The method of claim 13 wherein the chip and the substrate are separated by a gap about 25-50 microns wide.

21. The method of claim 13 wherein the underfill material is a thermo-set epoxy.

22. The method of claim 13 wherein the second material on top of said substrate and around the perimeter of said chip is a thermo-set epoxy.

23. The method of claim 13 wherein the underfill material between said chip and said substrate contains a gradient of filler material wherein the gradient of filler material varies between the concentration of filler material around the perimeter of said chip and the concentration of filler material at the center of said chip.

24. The method of claim 13 wherein the underfill material between said chip and said substrate contains a gradient of filler material after curing wherein the gradient of filler material varies between the concentration of filler material at the active surface of said chip and the concentration of filler material at the top of said substrate.

25. The method of claim 13 wherein the underfill material is dispensed prior to electrical bonding between said chip and said substrate and wherein the underfill material does not contain a filler material.

26. The method of claim 25 wherein the second material on top of said substrate and around the perimeter of said chip forms a fillet.

27. The method of claim 25 wherein the second material on top of said substrate and around the perimeter of said chip contains about 30-85% by weight of filler material.

28. The method of claim 27 wherein the second material on top of substrate and around the perimeter of said chip contains about 60-80% by weight of filler material.

29. The method of claim 27 wherein the filler material is alumina or silica.

30. The method of claim 25 wherein the chip and the substrate are separated by a gap about 25-50 microns wide.

31. The method of claim 25 wherein the underfill material is a thermo-set epoxy.

32. The method of claim 25 wherein the second material on top of said substrate and around the perimeter of said chip is a thermo-set epoxy.