Voltage level shifting circuit for bidirectional data

• US 6,373,284 B1
• Filed: 08/14/2000
• Issued: 04/16/2002
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Nguyen, Quang, Delage, Christelle
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/637,685
• Time in Patent Office: 610 Days
• Field of Search: 326/80, 326/81, 326/62, 326/63, 326/21, 326/22, 326/23, 326/24, 326/25, 327/333, 327/391
• US Class Current: 326/80
• CPC Class Codes: H03K 19/018592 with a bidirectional operation

Abstract

A voltage leveling circuit (20) for use as a bi-directional device to translate logic states represented by a first voltage level to logic states represented by a second voltage level. Voltage leveling circuit uses pass transistor (34) and pass transistor (36) connected in a serial fashion to control current flow between the first data terminal (D₁) and the second data terminal (D₂). Once current flow is controlled, pull up resistors (46) and (52) are used to perform the voltage level shifting. Two stage ESD protection is provided for gate oxide regions of pass transistors (34) and (36). A control terminal(E₁) is provided to allow an external disable/enable signal to control the operation of voltage leveling circuit (20).

Claims

1. A level shifting circuit having first and second data terminals, comprising:

a first current switch having a first conduction terminal coupled to the first data terminal for receiving a signal defined to have a first state at a first level;

a second current switch having a first conduction terminal coupled to a second conduction terminal of the first current switch at a first node, a control electrode coupled to a bias terminal, and a second conduction terminal coupled to the second data terminal for providing the signal having the first state at a second level; and

a voltage clamping device having an input coupled to the control electrode of the second current switch and having an output coupled to a ground potential terminal.

2. The level shifting circuit of claim 1, wherein the first current switch includes a transistor having a first conduction terminal coupled to the first data terminal, a control terminal coupled for receiving a first threshold signal, and a second conduction terminal coupled to the first node.

3. The level shifting circuit of claim 2, wherein the transistor is a symmetrical, NMOS device.

4. The level shifting circuit of claim 2, wherein the second current switch includes a transistor having a first conduction terminal coupled to the first node, a control terminal coupled to the bias terminal for receiving a second threshold signal, and a second conduction terminal coupled to the second data terminal.

5. The level shifting circuit of claim 4, wherein the transistor is a symmetrical, NMOS device.

6. An integrated circuit, comprising:

a level shifting circuit for converting a signal from a first level to a second level, the level shifting circuit including,

(a) a first transistor having a first conduction terminal coupled for receiving the signal operating at the first level, a second conduction terminal coupled to a first node, and a control terminal coupled to a first bias terminal, and

(b) a second transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled for providing the signal operating at the second level, and a control terminal coupled to a second bias terminal;

a first current sink device having an input coupled to the first bias terminal and having an output coupled to a ground potential terminal;

a first voltage clamping device having an input coupled to the first bias terminal and having an output coupled to the ground potential terminal;

a second current sink device having an input coupled to the second bias terminal and having an output coupled to the ground potential terminal; and

a second voltage clamping device having an input coupled to the second bias terminal and having an output coupled to the ground potential terminal.

7. The integrated circuit of claim 6, further including a logic device coupled to receive an enable signal to provide an output signal to the control terminal of the first transistor.

8. A The integrated circuit of claim 6, wherein the first current sink device includes a transistor having a first conduction terminal coupled to the first bias terminal, and a control terminal and a second conduction terminal coupled together to the ground potential terminal.

9. The integrated circuit of claim 8, wherein the transistor is an NMOS device.

10. The integrated circuit of claim 6, wherein the first voltage clamping device includes a transistor having a first conduction terminal coupled to the first bias terminal, and a control terminal and a second conduction terminal coupled together to the ground potential terminal.

11. The integrated circuit of claim 10, wherein the transistor is an NMOS device.

12. The integrated circuit of claim 6, wherein the second current sink device includes a transistor having a first conduction terminal coupled to the second bias terminal, and a control terminal and a second conduction terminal coupled together to the ground potential terminal.

13. The integrated circuit of claim 12, wherein the transistor is an NMOS device.

14. The integrated circuit of claim 6, wherein the second voltage clamping device includes a transistor having a first conduction terminal coupled to the second bias terminal, and a control terminal and a second conduction terminal coupled together to the ground potential terminal.

15. The integrated circuit of claim 14, wherein the transistor is an NMOS device.