Fast-locking dual rail digital delayed locked loop

• US 6,373,301 B1
• Filed: 04/18/2001
• Issued: 04/16/2002
• Est. Priority Date: 04/18/2001
• Status: Expired due to Term

• Current Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Original Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Inventors: Chen, Han-Ning, Kuo, Jew-Yong, Lee, Ming-Shien, Chen, Tsan-Hui
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/836,244
• Time in Patent Office: 363 Days
• Field of Search: 327/141, 327/144, 327/145, 327/146, 327/147, 327/149, 327/150, 327/156, 327/158, 327/159, 327/77, 327/78, 327/392, 327/393, 327/398, 327/403
• US Class Current: 327/141
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There'"'"'s a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Claims

1. A circuit for generating a delay signal, comprising:

a first delay line, in response to an external clock signal and a first delay control signal, for generating a first delay signal;

a second delay line, in response to a second delay control signal and the external clock signal, for generating a second delay signal;

a delay unit, responsive to the external clock signal, for generating an internal delay signal;

a first phase detector, responsive to the internal delay signal and the first delay signal, for generating a first control signal;

a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal;

a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and

a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.

2. The circuit of claim 1, wherein the first delay line and the second delay line have N DTC delay units respectively, N is a predetermined number.

3. The circuit of claim 2, wherein N equals to 4.

4. The circuit of claim 1, wherein the internal delay signal generated by the delay unit has a delay of ½

Tres to the external clock signal, wherein Tres is a difference of timings of the first delay signal and the second delay signal.

5. The circuit of claim 1, wherein the delay unit is further responsive to the first delay signal and the second delay signal.

6. The circuit of claim 1, wherein the first delay control signal and the second delay control signal having initial values of k and k+1 respectively, k is a number, the delay line monitor generates the first and the second delay control signals by the steps of:

if the first control signal is 1 and the second control signal is 0, decreasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1; and

if the first control signal is 0 and the second control signal is 1, increasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1.

7. The circuit of claim 2, wherein the delay signal generated by the DTC delay unit has a delay of T/N to the external clock signal, T is a cycle time of the external clock signal.

8. The circuit of claim 3, the delay signal generated by the DTC delay unit has a delay of T/4 to the external clock signal.

9. The circuit of claim 1, wherein the first phased detector is a D flip-flop.

10. The circuit of claim 1, wherein the second phase detector is a D flip-flop.

11. A method for generating a delay signal, comprising the following steps:

(11.1) providing a first delay line, in response to an external clock signal and the first delay control signal, for generating a first delay signal;

(11.2) providing a second delay line, in response to a second delay control signal, for generating a second delay signal;

(11.3) providing a delay unit, responsive to the external clock signal, for generating an internal delay signal;

(11.4) providing a first phase detector, responsive to internal delay signal and the first delay signal, for generating a first control signal;

(11.5) providing a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal;

(11.6) providing a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and

(11.7) providing a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.

12. The method of claim 11, wherein the first delay line and the second delay line have N DTC delay units respectively, N is a predetermined number.

13. The method of claim 12, wherein N equals to 4.

14. The method of claim 11, wherein the internal delay signal generated by the delay unit has a delay of ½

Tres to the external clock signal, wherein Tres is a difference of timings of the first delay signal and the second delay signal.

15. The circuit of claim 11, wherein the delay unit is further responsive to the first delay signal and the second delay signal.

16. The method of claim 11, wherein the first delay control signal and the second delay control signal having initial values of k and k+1 respectively, k is a number, the delay line monitor generates the first and the second delay control signals by the steps of:

if the first control signal is 1 and the second control signal is 0, decreasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1; and

if the first control signal is 0 and the second control signal is 1, increasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1.

17. The method of claim 11, wherein the delay signal generated by the DTC delay unit has a delay of T/N to the external clock signal, T is a cycle time of the external clock signal, N is a predetermined number.

18. The method of claim 11, the delay signal generated by the DTC delay unit has a delay of T/4 to the external clock signal.

19. The method of claim 11, wherein the first phased detector is a D flip-flop.

20. The method of claim 11, wherein the second phased detector is a D flip-flop.