Digital cosine and sine multiplication circuits

• US 6,373,316 B1
• Filed: 01/18/2000
• Issued: 04/16/2002
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wu, Miaochen
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/484,358
• Time in Patent Office: 819 Days
• Field of Search: 327/105, 327/107, 327/113, 327/114, 327/116, 327/119, 327/120, 327/121, 327/355, 327/356, 327/106, 365/7.8, 377/47, 377/48, 708/271, 708/272, 708/276
• US Class Current: 327/356
• CPC Class Codes: G06F 7/4812 Complex multiplication
• CPC Class Codes: G06F 7/548 Trigonometric functions; Co-ordinate transformations

Abstract

By sampling at six times the carrier frequency cosine and sine multiplication circuits are found to be constructable from simple shift and inversion circuit. Shifting and inversion are controlled by means of a simple finite state machine or other circuits cycling through a six cycle periodic sequence.

Claims

1. A digital cosine multiplication circuit comprising:

a digital shifting circuit receiving a sampled input signal;

a digital inverting circuit receiving sampled output signal from said digital shifting circuit;

control means for selecting either no shift or a single left shift for said digital shifting circuit and for selecting either no inversion or inversion for said inverting circuit, said shift and inversion selections being coordinated to produce a cosine multiplication of said sampled input signal.

2. The circuit of claim 1 further including a circuit for dividing the output of said inverter circuit in half.

3. The circuit of claim 2 in which said dividing circuit is a right shifter.

4. A digital cosine multiplication circuit comprising:

a digital shifting circuit receiving a sample input signal;

a digital inverting circuit receiving sampled output signals from said digital shifting circuit; and

means for coordinating said shifting circuit and said inverting circuit so as to effect a cosine multiplication of said input signal.

5. A digital cosine multiplication circuit comprising:

a digital left shift circuit for receiving a sampled input signal;

a first multiplexor for selecting for its output either the output of said left shift circuit or said sampled input signal;

a digital inverter circuit receiving the output of said first multiplexor;

a second multiplexor for selecting for its output either the output of said digital inverter circuit or the output of said first multiplexor;

means for controlling said multiplexor selection so as to effectuate multiplication of said sampled input signal by the cosine function.

6. The circuit of claim 5 further including a circuit for dividing the output of said second multiplexor circuit in half.

7. A digital sine multiplication circuit comprising:

a multiplexor for selecting for its output one of three choices of input selected from the group consisting of an inverted signal input, a non-inverted signal input and zero; and

a multiplexor controller which controls selection sequencing for said multiplexor so as to effectuate multiplication by the sine function.

8. The circuit of claim 7 further including a circuit for scaling the output of said multiplexor so that said sine multiplication is by a sine function with unit amplitude.

9. A digital cosine multiplication circuit comprising:

a first multiplexor for selecting between shifted and non-shifted versions of an input digital signal;

an inverter receiving the selected output from said inverter and the output from said first multiplexor;

a second multiplexor having as inputs the output from said inverter and the output from said first multiplexor; and

a multiplexor controller which controls output selection for said first and second multiplexors so as to effectuate multiplication by the cosine function.