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Integrated circuit defect review and classification process

  • US 6,373,566 B2
  • Filed: 04/20/2001
  • Issued: 04/16/2002
  • Est. Priority Date: 01/30/1997
  • Status: Expired due to Fees
First Claim
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1. A method by a user to evaluate a wafer of a plurality of wafers for defects in a plurality of manufacturing processes, each wafer of the plurality of wafers having integrated circuit semiconductor dice thereon, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having at least one circuit, said method comprising:

  • determining from historical information concerning at least one process of manufacture of integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on at least two dice of the integrated circuit semiconductor dice on the wafers, said at least one type of surface defect visible to a user visually inspecting the integrated circuit semiconductor dice on the wafers for at least one surface defect thereon and determining at least one subsequent failure of at least two dice having a surface defect thereon of the integrated circuit semiconductor dice on the wafers;

    visually inspecting at least two dice of integrated circuit semiconductor dice on a wafer to determine surface defects thereon by a user viewing said at least two dice of said integrated circuit semiconductor dice on said wafer, said surface defects including at least one defect of defects from bond pad formation problems and defects from incomplete formation of said at least one circuit of each of said at least two dice of said integrated circuit semiconductor dice on said wafer;

    selecting types of surface defects present on said at least two dice of said integrated circuit semiconductor dice on said wafer from the visual inspection of said at least two dice of said integrated circuit semiconductor dice on said wafer by the user viewing said at least two dice of said integrated circuit semiconductor dice on said wafer;

    selecting a range of sizes of said surface defects from the visual inspection of said at least two dice of said integrated circuit semiconductor dice on said wafer by the user;

    selecting a number of said integrated circuit semiconductor dice for visual inspection on said wafer by the user selecting at least one other die of said integrated circuit semiconductor dice on said wafer for the visual inspection thereof for surface defects thereon;

    summarizing the number, types, and range of sizes of the surface defects of said at least two dice and said at least one other die of said integrated circuit semiconductor dice on said wafer from a visual inspection of at least three dice of said integrated circuit semiconductor dice on said wafer by the user;

    comparing said number, types and ranges of sizes of the surface defects of said at least two dice and said at least one other die of said integrated circuit semiconductor dice on said wafer to the historical information concerning the at least one process of manufacture of integrated circuit semiconductor dice on wafers; and

    determining if said wafer is acceptable to proceed in said manufacturing process based upon the visual inspection of the at least three dice of said integrated circuit semiconductor dice on said wafer by the user and based upon the historical information concerning the at least one process of manufacture of integrated circuit semiconductor dice on wafers and the at least one relationship between the at least one type of surface defect on the at least two dice of the integrated circuit semiconductor dice on the wafers visible to the user visually inspecting the integrated circuit semiconductor dice on the wafers and the at least one subsequent failure of the at least two dice having the surface defect thereon of the integrated circuit semiconductor dice on the wafers.

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