Quad CAM cell with minimum cell size

• US 6,373,739 B1
• Filed: 12/06/2000
• Issued: 04/16/2002
• Est. Priority Date: 12/06/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Lien, Chuen-Der, Wu, Chau-Chin
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/731,160
• Time in Patent Office: 496 Days
• Field of Search: 365/49, 365/189.07, 365/168, 711/108
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A four-state (quad) CAM cell that stores one of four logic values: a logic high value, a logic low value, a logic high don'"'"'t care value, and a logic low don'"'"'t care value. Each quad CAM cell includes a first memory cell, a second memory cell, a comparator circuit, and a control switch. The first memory cell stores a data value (i.e., logic high value or logic low value), and transmits this stored data value to the comparator circuit. The second memory cell stores a care/don'"'"'t care data value that is transmitted to the control switch. Portions of the comparator circuit and the control switch form a discharge path between a match line and a discharge line connected to the quad CAM cell. The control switch is controlled by the care/don'"'"'t care value to open/close a first part of the discharge path. The comparator circuit is controlled to open a second part of the discharge path when, for example, the stored data value is equal to an applied data value.

Claims

1. A quad CAM cell comprising:

a first memory cell for storing a stored data value;

a comparator circuit having a first control terminal connected to the first memory cell and a second control terminal connected to receive an applied data value;

a second memory cell for storing a care/don'"'"'t care data value; and

a control switch connected in series with the comparator switch between a match line and a discharge line, the control switch having a control terminal connected to the second memory cell;

wherein, during a compare operation, the comparator circuit and the control switch selectively opens a path between the match line and the discharge line when the applied data value fails to match the stored data value, and the care/don'"'"'t care data value is equal to a predetermined value.

2. The quad CAM cell according to claim 1, wherein the first memory cell comprises an SRAM cell including a latch for storing the stored data value at a first node, and an inverse of the stored data value at a second node.

3. The quad CAM cell according to claim 2, wherein the SRAM cell further comprises:

a first p-channel transistor connected between a first voltage source and the second node, the first p-channel transistor having a gate terminal connected to the first node;

a second p-channel transistor connected between the first voltage source and the first node, the second p-channel transistor having a gate terminal connected to the second node;

a first n-channel transistor connected between a second voltage source and the second node, the first n-channel transistor having a gate terminal connected to the first node;

a second n-channel transistor connected between the second voltage source and the first node, the second n-channel transistor having a gate terminal connected to the second node;

a first access transistor connected between a first data line and the first node, the first pass transistor having a gate terminal connected to a word line; and

a second access transistor connected between a second data line and the second node, the second pass transistor having a gate terminal connected to the word line.

4. The quad CAM cell according to claim 2, wherein the comparator circuit comprises:

a first pass transistor having a gate terminal connected receive the applied data signal; and

a second pass transistor connected in series with the first pass transistor and having a gate terminal connected to the second node.

5. The quad CAM cell according to claim 4, wherein the control switch comprises a third pass transistor connected between the comparator circuit and the match line.

6. The quad CAM cell according to claim 5, wherein the comparator circuit further comprises:

a fourth pass transistor having a gate terminal connected to receive an inverse of the applied data signal; and

a fifth pass transistor connected in series with the third pass transistor and having a gate terminal connected to the first node,

wherein the fourth pass transistor and the fifth pass transistor are connected in parallel with the first pass transistor and the second pass transistor between the control switch and the discharge line.

7. The quad CAM cell according to claim 4, wherein the control switch comprises a third pass transistor connected between the comparator circuit and the discharge line.

8. The quad CAM cell according to claim 7, wherein the comparator circuit further comprises:

a fourth pass transistor having a gate terminal connected receive an inverse of the applied data signal; and

a fifth pass transistor connected in series with the third pass transistor and having a gate terminal connected to the first node,

wherein the fourth pass transistor and the fifth pass transistor are connected in parallel with the first pass transistor and the second pass transistor between the control switch and the match line.

9. The quad CAM cell according to claim 2,

wherein the comparator circuit comprises:

a first pass transistor having a gate terminal connected receive the applied data signal; and

a second pass transistor having a gate terminal connected to the second node, and

wherein the control switch is connected in series between the first pass transistor and the second pass transistor.

10. The quad CAM cell according to claim 9,

wherein the first pass transistor is connected between the control switch and the discharge line, and

wherein the second pass transistor is connected between the control switch and the match line.

11. The quad CAM cell according to claim 10, wherein the comparator circuit further comprises:

a fourth pass transistor having a gate terminal connected receive an inverse of the applied data signal, the fourth pass transistor being connected in parallel with the first pass transistor between the control switch and the discharge line; and

a fifth pass transistor having a gate terminal connected to the first node, the fifth pass transistor being connected in parallel with the second pass transistor between the control switch and the match line.

12. The quad CAM cell according to claim 2, wherein the comparator circuit comprises:

a first pass transistor having a gate terminal connected the second node, a first terminal connected to receive the first data signal, and a second terminal,

a second pass transistor having a gate terminal connected to the first node, a first terminal connected to receive the first data signal, and a second terminal; and

a third pass transistor having a gate terminal to the second terminals of the first and second pass transistors,

wherein the third pass transistor is connected in series with the control switch between the match line and the discharge line.

13. The quad CAM cell according to claim 2, the control switch comprises a fourth pass transistor connected between the third pass transistor and the match line.

14. The quad CAM cell according to claim 1, wherein the second memory cell comprises an SRAM cell.

15. The quad CAM cell according to claim 1, wherein the second memory cell comprises a non-volatile memory cell.

16. A CAM cell array comprising a plurality of quad CAM cells arranged in rows and columns, each row of quad CAM cells being connected to an associated match line, and each column of quad CAM cells being connected to an associated data line, wherein each quad CAM cell comprises:

a first memory cell for storing a stored data value;

a comparator circuit having a first control terminal connected to the first memory cell and a second control terminal connected to the associated data line;

a second memory cell for storing a care/don'"'"'t care data value; and

a control switch connected in series with the comparator switch between the associated match line and a discharge line, the control switch having a control terminal connected to the second memory cell;

wherein, during a compare operation, the comparator circuit and the control switch open a path between the associated match line and the discharge line only when an applied data value transmitted on the associated data line is equal to the stored data value, thereby turning on the comparator circuit, and the care/don'"'"'t care data value is equal to a predetermined value that turns on the control switch.

17. The CAM cell array according to claim 16, wherein each quad CAM cell further comprises:

a second data memory cell for storing a second stored data value;

a second comparator circuit having a control terminal connected to the second data memory cell; and

a second control switch connected in series with the second comparator circuit between a second match line and a second discharge line,

wherein the second control switch includes a control terminal connected to the mask memory cell.

18. The CAM cell array according to claim 16, wherein each quad CAM cell further comprises:

a second data memory cell for storing a second stored data value;

a second comparator circuit having a control terminal connected to the second data memory cell; and

a second control switch connected in series with the second comparator circuit between the associated match line and the discharge line,

wherein the second control switch includes a control terminal connected to the mask memory cell.

19. A CAM cell array comprising a plurality of quad CAM cells arranged in rows and columns, each row of quad CAM cells being connected to an associated match line, and each column of quad CAM cells being connected to an associated data line, wherein each quad CAM cell comprises:

a memory cell for storing a stored data value;

comparator means for comparing the stored data value with an applied data value transmitted on the associated data line, and for opening a first part of a signal path between the associated match line and the discharge line only when the stored data value fails to match the applied data value; and

control means connected in series with the comparator means for receiving a care/don'"'"'t care data value, and for opening a second part of a signal path between the associated match line and the discharge line only when the care/don'"'"'t care data value is equal to a predetermined data value.

20. The CAM cell array according to claim 19, further comprising a mask memory cell for storing the care/don'"'"'t care data value.