Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells

• US 6,373,746 B1
• Filed: 09/22/2000
• Issued: 04/16/2002
• Est. Priority Date: 09/28/1999
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu, Shibata, Noboru
• Primary Examiner(s): Ho, Hoai V.
• Application Number:
  US09/667,610
• Time in Patent Office: 571 Days
• Field of Search: 365/185.03, 365/185.08, 365/185.25, 365/185.01
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2211/5649 Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

Claims

1. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor storing first data, and a first latch circuit storing second data, both being located at one end of the bit line.

2. The nonvolatile semiconductor memory according to claim 1, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

3. The nonvolatile semiconductor memory according to claim 2, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

4. The nonvolatile semiconductor memory according to claim 3, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

5. The nonvolatile semiconductor memory according to claim 1, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

6. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor storing first data, and a first latch circuit storing second data, both being located at one end of the bit lie.

7. The nonvolatile semiconductor memory according to claim 6, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

8. The nonvolatile semiconductor memory according to claim 7, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

9. The nonvolatile semiconductor memory according to claim 8, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

10. The nonvolatile semiconductor memory according to claim 6, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

11. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor and a first latch circuit, both being located at one end of the bit line, and

a program operation to said memory cell is executed based on a first data stored in said first capacitor and second data stored in said first latch circuit.

12. The nonvolatile semiconductor memory according to claim 11, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

13. The nonvolatile semiconductor memory according to claim 12, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

14. The nonvolatile semiconductor memory according to claim 13, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

15. The nonvolatile semiconductor memory according to claim 11, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

16. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor and a first latch circuit, both being located at one end of the bit line, and

a program operation to said memory cell is executed based on first data read from said memory cell and stored in said first capacitor and second data input from outside the chip, on which said memory cell section is formed, and stored in said first latch circuit.

17. The nonvolatile semiconductor memory according to claim 16, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

18. The nonvolatile semiconductor memory according to claim 17, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

19. The nonvolatile semiconductor memory according to claim 18, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

20. The nonvolatile semiconductor memory according to claim 16, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

21. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor and a first latch circuit,

a first program operation and a second program operation are carried out to store first data and second data in said memory cell,

in said first program operation, said first data is programmed to said memory cell based on said first data stored in said first latch circuit, and

in said second program operation, said first and second data are stored in said memory cell based on said second data stored in said first latch circuit and said first data read from said memory cell and stored in said first capacitor.

22. The nonvolatile semiconductor memory according to claim 21, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

23. The nonvolatile semiconductor memory according to claim 22, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

24. The nonvolatile semiconductor memory according to claim 23, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

25. The nonvolatile semiconductor memory according to claim 21, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

26. A nonvolatile semiconductor memory comprising:

a memory cell section storing data having n values, where n is a natural number of not higher than 3, said memory cell including a memory cell set at a “

1”

state in which the memory cell has a first threshold level, a “

2”

state in which the memory cell has a second threshold level, . . . and an “

n”

state in which the memory cell has an n-th threshold level according to a value of said data;

a bit line connected to said memory cell section; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two bits or more;

wherein said data circuit includes a first capacitor and a first latch circuit, 1a first program operation and a second program operation are conducted to store first data and second data in said memory cell, 1in said first program operation, said memory cell is set at one of said “

1”

state, said “

2”

state, . . . and an “

m”

state, where m<

n, based on said first data stored in said first latch circuit, and

in said second program operation, said memory cell is set at one of said “

1”

state, said “

2”

state, . . . and a “

k”

state, where m>

k>

n, based on said second data stored in said first latch circuit and said first data read from said memory cell and stored in said first capacitor.

27. The nonvolatile semiconductor memory according to claim 26, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

28. The nonvolatile semiconductor memory according to claim 27, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

29. The nonvolatile semiconductor memory according to claim 28, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

30. The nonvolatile semiconductor memory according to claim 26, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

31. A nonvolatile semiconductor memory comprising:

a first memory cell section including a first memory cell;

a second memory cell section including a second memory cell;

a bit line connected to said first and second memory cell sections; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two bits or more;

wherein said data circuit includes a first capacitor storing first data written into or read from said first memory cell, and a first latch circuit storing second data written into or read from said second memory cell, both being located at one end of the bit line.

32. The nonvolatile semiconductor memory according to claim 31, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

33. The nonvolatile semiconductor memory according to claim 32, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

34. The nonvolatile semiconductor memory according to claim 33, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

35. The nonvolatile semiconductor memory according to claim 31, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

36. A nonvolatile semiconductor memory comprising:

a first memory cell section including a first memory cell;

a second memory cell section including a second memory cell;

a bit line connected to said first and second memory cell sections; and

a data circuit connected to said bit line, said data circuit temporarily storing program/read data having two bits or more;

wherein said data circuit includes a first capacitor and a first latch circuit, both being located at one end of the bit line,

in a second program operation to said second memory cell, said first capacitor stores first data, said second program operation conducted based on second data stored in said first latch circuit;

in a first program operation to said first memory cell, said first data stored in said first capacitor is transferred to said first latch circuit, said first program operation conducted based on said first data stored in said first latch circuit.

37. The nonvolatile semiconductor memory according to claim 36, further comprising a refresh circuit configured to refresh data stored in said first capacitor.

38. The nonvolatile semiconductor memory according to claim 37, wherein

said refresh circuit transfers the data stored in said first latch circuit to said bit line; and

said refresh circuit refreshes the data stored in said first capacitor using said first latch circuit while said data stored in said first latch circuit is held by said bit line, and then transfers said data held by said bit line to said first latch circuit.

39. The nonvolatile semiconductor memory according to claim 38, wherein said data stored in said first capacitor is refreshed while a program pulse is being supplied to said memory cell or after supply of said program pulse ends.

40. The nonvolatile semiconductor memory according to claim 36, wherein said memory cell is one of a plurality of memory cells constituting an NAND cell unit.

41. A nonvolatile semiconductor memory comprising:

a first memory cell section including a first memory cell;

a second memory cell section including a second memory cell;

a bit line connected to said first and second memory cell sections; and

a data circuit connected to one end of said bit line, said data circuit temporarily strong program/read data;

wherein said data circuit includes a first storage circuit configured to store data written into or read from said first memory cell, and a second storage circuit configured to store data written into or read from said second memory cell.

43. The nonvolatile semiconductor memory according to claim 41, wherein

both of said first and second storage circuits are latch circuits.

44. The nonvolatile semiconductor memory according to claim 41, wherein

said first and second memory cells are connected to different word lines.

42. The nonvolatile semiconductor memory according to claim 61, wherein

said first storage circuit is a capacitor, and said second storage circuit is a latch circuit.

45. A nonvolatile semiconductor memory comprising:

a first memory cell section including a first memory cell;

a second memory cell section including a second memory cell;

a bit line connected to said first and second memory cell sections; and

a data circuit connected to one end of said bit line, said data circuit temporarily storing program/read data;

wherein said data circuit includes first and second storage means;

if said second memory cell is programmed, said first storage means stores first data and said second memory cell is programmed based on second data stored in said second storage means; and

after second memory cell is been programmed, said first data held by said first storage means is transferred to said second storage means; and

said first memory cell is programmed based on said first data stored in said second storage means.

46. The nonvolatile semiconductor memory according to claim 45, wherein

said first storage circuit is a capacitor, and said second storage circuit is a latch circuit.

47. The nonvolatile semiconductor memory according to claim 45, wherein

both of said first and second storage circuits are latch circuits.

48. The nonvolatile semiconductor memory according to claim 45, wherein

said first and second memory cells are connected to different word lines.

49. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell;

a bit line connected to said memory section;

a transfer gate connected to one end of said bit line; and

a data circuit connected to said bit line through said transfer gate, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor storing first data, and a first latch circuit storing second data.

50. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory section;

a transfer gate connected to one end of said bit line; and

a data circuit connected to said bit line through said transfer gate, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor storing first data, and a first latch circuit storing second data.

51. A nonvolatile semiconductor memory comprising;

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory section;

a transfer gate connected to one end of said bit line; and

a data circuit connected to said bit line through said transfer gate, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor and a first latch circuit, and a program operation to said memory cell is executed based on a first data stored in said first capacitor and second data stored in said first latch circuit.

52. A nonvolatile semiconductor memory comprising:

a memory cell section including a memory cell storing data having three or more values;

a bit line connected to said memory section;

a transfer gate connected to one end of said bit line; and

a data circuit connected to said bit line through said transfer gate, said data circuit temporarily storing program/read data having two or more bits;

wherein said data circuit includes a first capacitor and a first latch circuit, and

a program operation to said memory cell is executed based on a first data read from said memory cell and stored in said first capacitor and second data input from outside the chip, on which said memory cell section is formed, stored in said first latch circuit.