Single chip networking device with enhanced memory access co-processor

• US 6,373,846 B1
• Filed: 03/09/1998
• Issued: 04/16/2002
• Est. Priority Date: 03/07/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Varma, Subir, Daniel, Thomas, Nattkemper, Dieter
• Primary Examiner(s): YAO, KWANG BIN
• Application Number:
  US09/036,966
• Time in Patent Office: 1,499 Days
• Field of Search: 370/382, 370/395, 370/397, 370/399, 370/409, 370/410, 370/419, 370/462, 370/463, 370/474, 370/395.1, 370/395.6, 370/395.61, 370/395.65, 370/428, 370/429, 712/1, 712/21, 710/52, 709/200
• US Class Current: 370/395.65
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU'"'"'s) in the ATM system. Thus, the APU is freed from doing respective data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Claims

1. A communications single chip device for use in a communication system network that transfers data packets, each of the data packets characterized by having a header and a trailer, said device residing on a single chip, comprising:

a programmable processor;

an input/output interface unit for communicating said device with a communication network, said input/output interface unit operatively connected to said programmable processor;

an Enhanced Direct memory Access (EDMA) unit, said EDMA a coprocessor to said programmable processor, said EDMA capable of removing headers and trailers from data packets, said EDMA capable of adding headers and trailers to data to form data packets, said EDMA capable of operating in at least two modes of operation, wherein the modes of operation further comprise one or more of the group consisting of direct memory access mode, ATM adaptation layer 0 mode, and ATM adaptation layer 5 mode;

at least one memory unit operatively connected to said programmable processor and EDMA;

a cell buffer memory (CBM) operatively connected to said interface unit for receiving data relating to packets;

said programmable processor, interface unit, EDMA, memory unit and CBM formed and residing on a single chip.

2. The communications device of claim 1 wherein the data packets comprise asynchronous transfer mode (ATM) cells, the programmable processor comprises an ATM processing unit (APU), and the input/output cell interface unit comprises an ATM cell interface unit (ACI).

3. The single chip ATM communication device of claim 2, wherein:

said APU and EDMA cooperate with said memory unit to initialize, send and receive data from data structures resident in said memory unit, said memory-resident data structures comprising a Virtual Connector Descriptor (VCD) and a Buffer Descriptor (BFD), said VCD and BFD containing data relating to virtual connections of ATM cells and to memory locations and the contents of memory locations of said CBM.

4. The single chip ATM communication device of claim 2, further comprising:

a scheduler unit and a timer unit, said scheduler unit and said timer unit cooperating with and under the control of said APU, and operatively connected to a memory, said scheduler and timer memory containing data relating to virtual connections of ATM cells and to provide APU with data relating to time; and

said scheduler and timer unit residing on said single chip.

5. The single chip ATM communication device of claim 4, wherein:

said scheduler and timer memory contains a calendar table data structure, said calendar table data strucuture containing data relating to a predetermined time interval for a particular list of virtual circuits, said calendar table data structure being a circular array;

said ACI comprising a Cell Buffer Manager (CBMa) having a plurality of registers which point to memory locations within the CBM, said CBM memory containing said ATM cell data in a linked-list data structure.

6. The communications device of claim 2 wherein the EDMA is capable of performing partial segmentation and reassembly.

7. The communications device of claim 2 wherein the EDMA is capable of performing complete segmentation and reassembly.

8. The communications device of claim 1 wherein the EDMA is capable of computing and inserting packet checksums.

9. The communications device of claim 8 wherein the packet checksums are based on a cyclical redundancy code.

10. The communications device of claim 1 wherein the EDMA is capable of computing and verifying packet checksums.

11. The communications device of claim 10 wherein the packet checksums are based on a cyclical redundancy code.

12. A method for processing ATM cells in an asynchronous transfer mode communications system network device for receiving, processing, and transmitting a plurality of data cells, said device residing on a single communications chip, said method comprising:

providing, on a single chip, a cell buffer memory unit including a memory means for receiving, storing, and recovering the ATM communication system data cells;

providing, on a single chip, a cell buffer memory manager communicating with said cell buffer memory unit;

providing, on a single chip, input/output (I/O) port interface means for communicating said device with an ATM communication system network, and causing said I/O port interface means to issue a respective request for access to said memory means;

providing, on a single chip, a programmable processor and a coprocessor, said processor exercising control over said coprocessor, said programmable processor and coprocessor residing on a single chip and cooperating with cell buffer memory unit memory means to initialize, send and receive data from data structures resident in said memory unit;

configuring said coprocessor to segment and reassemble ATM data cells in said memory means and to operate in at least two modes of operation, wherein the modes of operation comprise one or more of the group consisting of direct memory access mode, ATM adaptation layer 0 mode, and ATM adaptation layer 5 mode, said coprocessor accessing said memory means through said cell buffer memory manager,

whereby all steps of said method of processing ATM cells are performed by circuitry residing on a single communication circuit chip.