Single-chip audio circuitry, method, and systems using the same

• US 6,373,954 B1
• Filed: 10/14/1997
• Issued: 04/16/2002
• Est. Priority Date: 10/14/1997
• Status: Expired due to Term

• Current Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Gentry, Mark, Malcolm, Ronald D. Jr., Matthews, Phillip, Klaas, Jeff
• Primary Examiner(s): Mei, Xu
• Application Number:
  US08/949,563
• Time in Patent Office: 1,645 Days
• Field of Search: 381/119, 381/22, 381/23, 381/1, 381/17, 381/18, 381/19, 369/4, 700/94, 341/110, 341/126, 341/144
• US Class Current: 381/119
• CPC Class Codes: G06F 3/162 Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H04H 60/04 Studio equipment; Interconnection of studios
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Claims

1. A single-chip audio system comprising:

a bus interface;

digital to analog converters for converting digital audio data received through said bus to analog signals comprising;

first selectable digital to analog converters for selectively converting higher sound quality digital signals; and

second selectable digital to analog converters for selectively converting lower sound quality digital signals;

an analog mixer for mixing signals received from said digital to analog converters with an analog signal received from an external source and outputting first and second mixed signals in response; and

analog spatial enhancement circuitry for enhancing said first and second mixed analog signals output from said analog mixer.

2. The system of claim 1 wherein said higher quality sound digital signals are received through said bus interface.

3. The audio system of claim 2 wherein said bus interface intrefaces with an ISA.

4. The system of claim 1 wherein said lower quality sound digital signals are received by said second digital to analog converters from an on chip FM synthesizer.

5. The system of claim 1 wherein said lower quality sound digital signals are received by said second digital to analog converters from an external wavetable device.

6. The system of claim 1 wherein said analog spatial enhancement circuitry comprises:

a difference amplifier for generating a difference signal from said first and second mixed signals output from said mixer;

a filter for generating an acoustic crosstalk compensation signal from said difference signal;

an inverter for inverting said compensation signal;

a first summer for summing said inverted compensation signal with said first signal; and

a second summer for summing said compensation signal with said second signal.

7. The system of claim 1 and further comprising:

mute controls for muting said first and second mixed signals output from said mixer; and

circuitry for idling said digital to analog converters when said muting controls are asserted.

8. The system of claim 7 and further comprising circuitry for idling said mixer when said mute controls are asserted.

9. The system of claim 1 wherein said higher sound quality digital signals comprise digital words of a first bit-width and said lower sound quality signals comprise digital words of a second bit-width, said first bit-width being greater than said second bit-width.

10. The system of claim 9 wherein said first bit-width is 16 bits and said second bit-width is 12 bits.

11. The system of claim 1 wherein said first selectable digital to analog converters comprise delta-sigma converters.

12. The system of claim 11 wherein said delta-sigma converter comprises a 1-bit delta-sigma converter.

13. The system of claim 1 wherein said second selectable digital to analog converters comprise R-2R parallel converters.