Error checking of simulated printed images with process window effects included
First Claim
Patent Images
1. A method for checking integrated circuit designs for design rule violations comprising:
- generating an ideal simulated image based on said semiconductor designs;
altering said ideal simulated image to include potential manufacturing variations, thereby producing at least two simulated production images representing different manufacturing qualities; and
comparing said simulated production images to design rules to produce an error list.
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Abstract
A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
91 Citations
25 Claims
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1. A method for checking integrated circuit designs for design rule violations comprising:
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generating an ideal simulated image based on said semiconductor designs;
altering said ideal simulated image to include potential manufacturing variations, thereby producing at least two simulated production images representing different manufacturing qualities; and
comparing said simulated production images to design rules to produce an error list. - View Dependent Claims (2, 3, 4, 5, 6, 7)
comparing one or more of said production images within each given set to said design rules; and
comparing one or more of said sets of production images to said design rules.
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6. The method in claim 1, wherein said potential manufacturing variations include one or more of focus variations, exposure variations, deposition variations, etching variations, and alignment variations.
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7. The method in claim 1, wherein said design rules check one or more of spacing, intersection area, common run lengths and overlapping.
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8. A method of designing an integrated circuit comprising:
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referring to a design manual to prepare design data sets;
applying optical correction rules to said design data sets;
applying shapes adjustment rules to set design data sets;
applying process window variations to set design data sets;
comparing said design data sets, modified by said applying processes, to design rules; and
producing an error list for ones of said design data sets which violate said design rules. - View Dependent Claims (9, 10, 11, 12, 13, 14)
comparing one or more of said production images within each given set of production images to said design rules; and
comparing one or more of said sets of production images to said design rules.
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13. The method in claim 8, wherein said process window variations include one or more of focus variations, exposure variations, deposition variations, etching variations, and alignment variations.
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14. The method in claim 8, wherein said design rules check one or more of spacing, intersection area, common run lengths and overlapping.
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15. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method for checking integrated circuit designs for design rule violations, said method comprising:
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generating an ideal simulated image based on said semiconductor designs;
altering said ideal simulated image to include potential manufacturing variations, thereby producing at least two simulated production images representing different manufacturing qualities; and
comparing said production images to design rules to produce an error list. - View Dependent Claims (16, 17, 18, 19, 20, 21)
comparing one or more of said production images within each given set to said design rules; and
comparing one or more of said sets of production images to said design rules.
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20. The program storage device in claim 15, wherein said potential manufacturing variations include one or more of focus variations, exposure variations, deposition variations, etching variations, and alignment variations.
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21. The program storage device in claim 15, wherein said design rules check one or more of spacing, intersection area, common run lengths and overlapping.
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22. A computer system comprising at least one central processing unit, at least one input device, at least one output device and at least one storage device, said storage device tangibly embodying a program of instructions executable by the central processing unit to perform a method for checking integrated circuit designs for design rule violations, said method comprising:
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generating an ideal simulated image based on said semiconductor designs;
altering said ideal simulated image to include potential manufacturing variations, thereby producing at least two simulated production images representing different manufacturing qualities; and
comparing said production images to design rules to produce an error list. - View Dependent Claims (23, 24, 25)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsConrad, Edward W., Leipold, William C., Bula, Orest, Cole, Daniel C.
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Primary Examiner(s)Johns, Andrew W.
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Assistant Examiner(s)AZARIAN, SEYED H
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Application NumberUS09/237,148Time in Patent Office1,177 DaysField of Search382/144, 382/141, 382/142, 382/143, 382/145, 382/147, 382/152, 382/219, 382/205, 438/8, 438/800US Class Current382/144CPC Class CodesG03F 1/36 Masks having proximity corr...G06T 2207/30148 Semiconductor; IC; WaferG06T 7/0006 using a design-rule based a...
