Method of modeling circuit cells with distributed serial loads

• US 6,374,203 B1
• Filed: 02/05/1996
• Issued: 04/16/2002
• Est. Priority Date: 02/05/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wloka, Markus, Millman, Steven D., Tyler, Sean C.
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/596,857
• Time in Patent Office: 2,262 Days
• Field of Search: 395/500, 364/488-491, 364/578, 703/14, 716/17
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A plurality of serially coupled circuit cells (12-20) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance (22) and resistance (24, of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells (16-20). The distributed serial load is also applicable to portions of circuit cells (38,40) that are not be buffered and where the downstream loading has an effect on previous circuit drivers (14).

Claims

1. A method of modeling loading of a plurality of serially coupled circuit cells, comprising the steps of:

identifying effective load impedances for each of the plurality of serially coupled circuit cells where the circuit cells include active elements; and

forming a distributed serial load with said effective load impedances where said distributed serial load provides a load model of the plurality of serially coupled circuit cells.

2. The method of claim 1 wherein said step of identifying effective load impedances includes the step of providing a first capacitance for a first one of the plurality of serially coupled circuit cells.

3. The method of claim 2 wherein said step of identifying effective load impedances further includes the step of providing a first resistance for said first one of the plurality of serially coupled circuit cells.

4. The method of claim 3 wherein said step of providing a first capacitance includes the step of providing said first capacitance between an input node of said first one of the plurality of serially coupled circuit cells and a ground conductor.

5. The method of claim 4 wherein said step of providing a first resistance includes the step of providing said first resistance between said input node of said first one of the plurality of serially coupled circuit cells and an output node of said first one of the plurality of serially coupled circuit cells.

6. The method of claim 5 wherein said step of identifying effective load impedances further includes the step of providing a second capacitance for a second one of the plurality of serially coupled circuit cells.

7. The method of claim 6 wherein said step of identifying effective load impedances further includes the step of providing a second resistance for said second one of the plurality of serially coupled circuit cells.

8. The method of claim 7 wherein said step of providing a second capacitance includes the step of providing said second capacitance between an input node of said second one of the plurality of serially coupled circuit cells and said ground conductor.

9. The method of claim 8 wherein said step of providing a second resistor includes the step of providing said second resistance between said input node of said second one of the plurality of serially coupled circuit cells and an output node of said second one of the plurality of serially coupled circuit cells.

10. A method of simulating characteristics of a plurality of serially coupled circuit cells, comprising the steps of:

providing a first load for a first one of the plurality of serially coupled circuit cells where the circuit cells include active elements;

providing a second load for a second one of the plurality of serially coupled circuit cells where the circuit cells include active elements; and

forming a distributed serial load with said first and second loads of said first and second ones of the plurality of serially coupled circuit cells where said distributed serial load provides a characteristic load model of the plurality of serially coupled circuit cells.

11. The method of claim 10 wherein said step of providing a first load includes the step of providing a first capacitance between an input node of said first one of the plurality of serially coupled circuit cells and a ground conductor.

12. The method of claim 11 wherein said step of providing a first load further includes the step of providing a first resistance between said input node of said first one of the plurality of serially coupled circuit cells and an output node of said first one of the plurality of serially coupled circuit cells.

13. The method of claim 11 wherein said step of providing a second load includes the steps of:

providing a second capacitance between an input node of said second one of the plurality of serially coupled circuit cells and said ground conductor; and

providing a second resistance between said input node of said second one of the plurality of serially coupled circuit cells and an output node of said second one of the plurality of serially coupled circuit cells.

14. A method of simulating characteristics of a plurality of serially coupled circuit cells, comprising the steps of:

providing a first load for a first one of the plurality of serially coupled circuit cells where the circuit cells include active elements, wherein said step of providing a first load includes the step of providing a first transmission gate between an input node of said first one of the plurality of serially coupled circuit cells and an output node of said first one of the plurality of serially coupled circuit cells;

providing a second load for a second one of the plurality of serially coupled circuit cells where the circuit cells include active elements; and

forming a distributed serial load with said first and second loads of said first and second ones of the plurality of serially coupled circuit cells where said distributed serial load provides a characteristic load model of the plurality of serially coupled circuit cells.

15. The method of claim 14 wherein said step of providing a first load includes the step of providing a second transmission gate between an input node of said second one of the plurality of serially coupled circuit cells and an output node of said second one of the plurality of serially coupled circuit cells.

16. A method of modeling a memory array, comprising the steps of:

providing a first effective load impedance for a first bit cell of the memory arrays

providing a second effective load impedance for a second bit cell of the memory array, and

forming a distributed serial load with said first and second effective load impedances of said first and second bit cells where said distributed serial load provides a characteristic load model of the memory array.

17. The method of claim 16 wherein said step of providing a first effective load impedance includes the step of providing a first capacitance between an input node of said first bit cell and a ground conductor.

18. The method of claim 17 wherein said step of providing a first effective load impedance further includes the step of providing a first resistance between said input node of said first bit cell and an output node of said first bit cell.

19. The method of claim 18 wherein said step of providing a second effective load impedance includes the step of providing a second capacitance between an input node of said second bit cell and said ground conductor.

20. The method of claim 19 wherein said step of providing a second effective load impedance further includes the step of providing a second resistance between said input node of said second bit cell and an output node of said second bit cell.