Data pipelining method and apparatus for memory control circuit

• US 6,374,337 B1
• Filed: 11/16/1999
• Issued: 04/16/2002
• Est. Priority Date: 11/17/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/440,986
• Time in Patent Office: 882 Days
• Field of Search: 711/100, 711/102, 711/103, 711/104, 711/140, 711/154, 711/169, 365/189.01, 365/189.05
• US Class Current: 711/169
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register. When the data of the second data address is being accessed, the data in the first page register is transferred to a second page register. When the operation to read the data from the second data address is completed, the data can be placed in the first register. The data in the second page register can be rapidly transferred to a latch and on to a bus. In this manner, there is always space made available for the data read. Similarly, in a write operation, data is transferred from the data bus to the second page register and then to the first page register. The data in the first register is written into the memory array.

Claims

1. A nonvolatile memory control circuit for controlling reading and writing operations to and from a nonvolatile memory array, comprising:

a set of page registers having at least a first page register and a second page register for buffering data that is to be written to or read from a nonvolatile memory array;

said control circuit for receiving commands to operate said set of page registers for reading from and writing to said nonvolatile memory array;

a set of address latches coupled to the nonvolatile memory array, said set of address latches having at least a first address latch for receiving data addresses for addressing the nonvolatile memory array;

a state machine for operating said set of page registers and said address latches;

an address decoder for receiving and decoding data addresses to the nonvolatile memory array;

a state machine control logic for operating said machine in response to received commands; and

wherein during a current write command, data corresponding to the current write command is stored in said second page register while data corresponding to a previous write command is stored in the nonvolatile memory array from the first page register thereby creating a pipe-lining affect so as to expedite the performance of write operations to the nonvolatile memory array.

2. A nonvolatile memory control circuit as recited in claim 1 wherein during a first time period, said control circuit operates said set of address latches to have a first data address from said first address latch decoded for a read operation.

3. A nonvolatile memory control circuit as recited in claim 2 wherein, in a second time period, data read from said first data address of said memory array is fetched and placed in said first page register.

4. A nonvolatile memory control circuit as recited in claim 3 wherein, in said second time period, data in said first page register is transferred to a bus.

5. A nonvolatile memory control circuit as recited in claim 3 wherein said control circuit, in a second time period, operates said set of address latches to have a second data address from said second address latch decoded for a read operation.

6. A nonvolatile memory control circuit as recited in claim 5 wherein, in a third time period, data read from said second data address of said nonvolatile memory array is fetched and placed in said second page register.

7. A nonvolatile memory control circuit as recited in claim 1 wherein said control circuit, in a first time period, operates said set of address latches to have a first data address from said first address latch decoded for a write operation.

8. A nonvolatile memory control circuit as recited in claim 7 wherein, in a second time period, data stored in said first page register is placed in the nonvolatile memory array.

9. A nonvolatile memory control circuit as recited in claim 7 wherein said control circuitry, in said first time period, causes said first page register to store data to be stored in said memory array.

10. A nonvolatile memory control circuit as recited in claim 9 wherein said control circuit, in a second time period, operates said set of address latches to have a second data address from said second address latch decoded for a write operation.

11. A nonvolatile memory control circuit as recited in claim 10 wherein said control circuit, in said second time period, causes said second page register to store data to be stored in the nonvolatile memory array.

12. A nonvolatile memory control circuit for controlling reading and writing operations to and from a nonvolatile memory array, comprising:

a set of page registers coupled to a nonvolatile memory array, said set of page registers having at least a first page register and a second page register for buffering data that is to be written to or read from the nonvolatile memory array;

said control circuit for receiving commands to operate said set of page registers for reading from and writing to the nonvolatile memory array;

control circuitry coupled to said set of page registers and the nonvolatile memory array wherein during a current write command, data corresponding to said write command is stored in said second page register while data corresponding to a previous write command is being stored in the nonvolatile memory array from the first page register thereby creating a pipe-lining affect to expedite performing write operations on the nonvolatile memory array;

a set of address latches coupled to the nonvolatile memory array, said set of address latches having at least first address latch for receiving data addresses for addressing the nonvolatile memory array;

a state machine for operating said set of page registers and said address latches;

an address decoder for receiving and decoding data addresses to the nonvolatile memory array; and

a state machine control logic for operating said state machine in response to received commands.