Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction
First Claim
1. A circuit for controlling loading of instructions from an instruction cache to a pipeline in a computing system, said circuit including:
- branch control means for initiating a speculative preloading operation and/or an actual loading operation of a branch target instruction based on a branch prediction indicator;
monitoring means coupled to the branch control means for determining whether branch target instructions available for loading in the pipeline are invalid;
selecting means coupled to said branch control means and said monitoring means for selecting a replacement branch target instruction when an invalid branch target instruction is found, said replacement branch instruction being selected by ranking a number of potential branch target addresses when a speculative preloading operation is initiated;
loading means coupled to said branch control means, said monitoring means and said selecting means for (i) replacing said invalid branch target instruction with said replacement branch target instruction by causing said instruction cache to load said replacement branch target instruction for execution in the pipeline in response to initiation of said speculative preloading operation, and/or (ii) causing said instruction cache to load said branch target instruction for execution in the pipeline in response to initiation of said actual loading operation.
2 Assignments
0 Petitions
Accused Products
Abstract
An improved preload/prefetching architecture is disclosed for controlling branch target instruction loading in a pipelined processor. Branch target instructions can be speculatively preloaded/prefetched based on a first prediction indicator provided in a branch control instruction, and they also can be actually loaded/fetched based on a second prediction indicator provided in a branch instruction. This mechanism results in reduced cache latency during program execution. The preloading/prefetching of branch target instructions can also be prioritized under software control to optimize instruction execution, based on particular indicators specified for branch target instructions within a branch hint buffer.
23 Citations
20 Claims
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1. A circuit for controlling loading of instructions from an instruction cache to a pipeline in a computing system, said circuit including:
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branch control means for initiating a speculative preloading operation and/or an actual loading operation of a branch target instruction based on a branch prediction indicator;
monitoring means coupled to the branch control means for determining whether branch target instructions available for loading in the pipeline are invalid;
selecting means coupled to said branch control means and said monitoring means for selecting a replacement branch target instruction when an invalid branch target instruction is found, said replacement branch instruction being selected by ranking a number of potential branch target addresses when a speculative preloading operation is initiated;
loading means coupled to said branch control means, said monitoring means and said selecting means for (i) replacing said invalid branch target instruction with said replacement branch target instruction by causing said instruction cache to load said replacement branch target instruction for execution in the pipeline in response to initiation of said speculative preloading operation, and/or (ii) causing said instruction cache to load said branch target instruction for execution in the pipeline in response to initiation of said actual loading operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for controlling loading of instructions from an instruction cache to a pipeline in a computing system, the method including:
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(a) initiating a speculative preloading operation and/or an actual loading operation of a branch target instruction based on a branch prediction indicator; and
(b) determining whether branch target instructions available for loading in the pipeline are valid; and
(c) selecting a replacement branch target instruction when an invalid branch target instruction is found, said replacement branch instruction being selected by ranking a number of potential branch target addresses when a speculative preloading operation is initiated; and
(d) during a speculative loading operation, replacing said invalid branch target instruction with said replacement branch target instruction by causing said instruction cache to load said replacement branch target instruction for execution in the pipeline; and
(e) during an actual loading operation, causing said instruction cache to load said branch target instruction for execution in the pipeline. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification