Skew-insensitive low voltage differential receiver

• US 6,374,361 B1
• Filed: 04/22/1999
• Issued: 04/16/2002
• Est. Priority Date: 04/23/1998
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Jeong, Deog-Kyoon, Lee, Kyeongho
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/298,369
• Time in Patent Office: 1,090 Days
• Field of Search: 713/400, 713/401, 713/503, 713/600
• US Class Current: 713/503
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the converted full-swing clock signal, and a plurality of data recovery signals from the converted full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals. In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center position of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array.

Claims

1. An apparatus for correcting skew between high-speed differential swing data signals and an associated clock signal, the apparatus comprising:

a delay locked loop, coupled to the clock signal, for converting the clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the full-swing clock signal; and

data recovery channels, each data recovery channel coupled to a data signal and the plurality of clock recovery signals, comprising;

a converter for converting differential data signals into full-swing data signals;

a skew adjust circuit for adjusting the skew of the full-swing data signals;

a sampler array, coupled to the delay locked loop and the skew adjust circuit, for oversampling the full-swing data signals responsive to the plurality of clock signals and producing sampled data signals and lock signals; and

a phase adjusting circuit, coupled to the data recovery channels and the skew adjust circuit, for generating skew control signals to transmit to the skew adjust circuit responsive to the oversampled data signals and lock signals received from the sampler array.

2. The apparatus of claim 1 wherein the sampler array further comprises:

a plurality of transition sampling circuits for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled transition data signal responsive to the sampled transition;

a plurality of center sampling circuit for sampling a center point of each serial bit of data and generating a center sample signal responsive to the sample; and

the phase adjusting circuit for generating the skew control signals responsive to the center sample signals, lock signals, and sampled transition data signals received from the sampler array.

3. The apparatus of claim 2 further comprising:

a threshold bias circuit, for generating a high threshold signal, a low threshold signal, and a middle threshold signal having a voltage equal to an ideal logic threshold of a full swing data signal;

the center sampling circuits for comparing the voltage of the sampled center point of each serial bit of data to the middle threshold to generate a current skew signal and a next skew signal, wherein the skew signal is high responsive to the voltage of the sampled point exceeding the middle threshold signal; and

the transition sampling circuit for comparing the voltage of the sampled transition point to the middle transition for generating a lock signal responsive to the sampled voltage being between the high and low threshold voltages, and for generating a high signal responsive to the sampled voltage, and for generating a low signal responsive to the sampled voltage being less than the low threshold signal.

4. The apparatus of claim 2 wherein the phase adjusting circuit further comprises:

a plurality of phase detection cells, each cell coupled to one of the transition sampling circuits to receive a lock signal and a sampled transition data signal, and one of the center sampling circuits to receive a center sample signal, for generating an up-phase-adjust signal responsive to the lock signal indicating no lock, and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal, and for generating a down-phase-adjust signal responsive to the lock signal indicating no lock, and the transition data signal and center sample signal indicating the clock signal is lagging the data signal and generating a no-phase-adjust signal responsive to lock signal indicating a lock; and

a phase recommendation circuit, for comparing the plurality of up-phase-adjust signals, down-phase-adjust signals, and no-phase-adjust signals transmitted by the plurality of phase detection cells, to generate a phase recommendation signal.

5. An apparatus for correcting skew between low-voltage differential swing (LVDS) data signals and an LVDS clock signal, the apparatus comprising:

a delay locked loop, coupled to the LVDS clock signal, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the full-swing clock signal; and

data recovery channels, each data recovery channel coupled to a data signal and the plurality of clock recovery signals, comprising;

an LVDS converter for converting LVDS data signals into full-swing data signals;

a skew adjust circuit for adjusting the skew of the full-swing data signals;

a sampler array, coupled to the delay locked loop and the skew adjust circuit, for oversampling the full-swing data signals responsive to the plurality of clock signals and producing sampled data signals and lock signals; and

a phase adjusting circuit, coupled to the data recovery channels and the skew adjust circuit, for generating skew control signals to transmit to the skew adjust circuit responsive to the oversampled data signals and lock signals received from the sampler array.

6. The apparatus of claim 5 wherein the sampler array further comprises:

a plurality of transition sampling circuits for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled transition data signal responsive to the sampled transition; and

a plurality of center sampling circuit for sampling a center point of each serial bit of data and generating a center sample signal responsive to the sample; and

the phase adjusting circuit for generating the skew control signals responsive to the center sample signals, lock signals, and sampled transition data signals received from the sampler array.

7. The apparatus of claim 6 further comprising:

a threshold bias circuit for generating a high threshold signal, a low threshold signal, and a middle threshold signal having a voltage equal to an ideal logic threshold of a full swing data signal;

the center sampling circuits for comparing the voltage of the sampled center point of each serial bit of data to the middle threshold to generate a current skew signal and a next skew signal, wherein the skew signal is high responsive to the voltage of the sampled point exceeding the middle threshold signal; and

the transition sampling circuit for comparing the voltage of the sampled transition point to the middle transition for generating a lock signal responsive to the sampled voltage being between the high and low threshold voltages, and for generating a high signal responsive to the sampled voltage, and for generating a low signal responsive to the sampled voltage being less than the low threshold signal.

8. The apparatus of claim 6 wherein the phase adjusting circuit further comprises:

a plurality of phase detection cells, each cell coupled to one of the transition sampling circuits to receive a lock signal and a sampled transition data signal, and one of the center sampling circuits to receive a center sample signal, for generating an up-phase-adjust signal responsive to the lock signal indicating no lock, and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal, and for generating a downphase-adjust signal responsive to the lock signal indicating no lock, and the transition data signal and center sample signal indicating the clock signal is lagging the data signal, and generating a no-phase-adjust signal responsive to lock signal indicating a lock; and

a phase recommendation circuit for comparing the plurality of up-phase-adjust signals, down-phase-adjust signals, and no-phase-adjust signals transmitted by the plurality of phase detection cells, to generate a phase recommendation signal.

9. The apparatus of claim 5 further comprising:

a plurality of delay cells, coupled together serially, each cell for delaying a clock signal for half of a data cycle, for receiving the LVDS clock signal and generating a set of center clock signals and a set of transition clock signals.

10. The apparatus of claim 9, the plurality of delay cells further comprising:

a first buffer, coupled to the LVDS clock signal, for generating a first transition clock signal;

a first delay device coupled to the LVDS clock signal, for delaying the LVDS clock signal for a half of a clock cycle;

a second buffer, coupled to the first delay device, for receiving the delayed clock signal, and generating a first center clock signal; and

a second delay device, coupled to the first delay device, for delaying the LVDS clock signal for a half of a clock cycle;

a third buffer, coupled to the second delay cell, for generating a second transition clock signal; and

wherein delay devices and buffers are repeatedly coupled together to generate a plurality of transition and center clock signals.

11. The apparatus of claim 9, wherein the amount of delay provided by a delay cell is adjustable, further comprising:

a phase detector, coupled to a first center clock signal and a last center clock signal, for comparing rising edges of the clock signals and generating a shift down signal responsive to the rising edge of the last center clock signal leading the rising edge of the first center clock signal, generating a shift up signal responsive to the rising edge of the last center clock signal lagging the rising edge of the first center clock signal; and

a charge pump circuit, having an input coupled to the phase detector and an output coupled to the delay cells, for adjusting the delay of the delay cells responsive to receiving an shift up or shift down signal.

12. The apparatus of claim 9, further comprising:

a lock detector, coupled to a first center clock signal and a last center clock signal, for generating a lock signal responsive to detecting that a rising edge of the first center clock signal is synchronous with a rising edge of a last center clock signal, and for generating a no-lock signal otherwise.

13. The apparatus of claim 12, wherein the delay locked loop further comprises:

a replica skew circuit, having an input coupled to the LVDS clock signal and an output coupled to the plurality of delay cells, for adding a fixed amount of delay to the LVDS clock signal; and

the data recovery channels further comprising;

an initial bias circuit, coupled to the skew adjust circuit and the lock detecting circuit, for causing the skew adjust circuit to add a fixed amount of delay to the input data signal responsive to receiving a no-lock signal from the lock detecting circuit, wherein the fixed amount of delay added by the skew adjust circuit is equal to the fixed amount of delay added by the replica skew circuit.

14. An apparatus for correcting skew between a high-speed data signal and an associated clock signal, the apparatus comprising:

a delay locked loop, coupled to the clock signal, for generating a plurality of clock recovery signals from the clock signal; and

a data recovery channel, coupled to the data signal and the plurality of clock recovery signals, comprising;

a skew adjust circuit, for adjusting the skew of the full-swing data signals;

a sampler array, coupled to the delay locked loop and the skew adjust circuit, for oversampling the data signal responsive to the plurality of clock signals and producing sampled data signals and lock signals; and

a phase adjusting circuit, coupled to the data recovery channels and the skew adjust circuit, for generating skew control signals to transmit to the skew adjust circuit responsive to the oversampled data signal and lock signal received from the sampler array.

15. The apparatus of claim 14 wherein the sampler array further comprises:

a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled transition data signal responsive to the sampled transition;

a center sampling circuit, for sampling a center point of each serial bit of data and generating a center sample signal responsive to the sample; and

the phase adjusting circuit generating skew control signals responsive to the center sample signal, lock signal, and sampled transition data signal received from the sampler array.

16. The apparatus of claim 15 wherein the phase adjusting circuit further comprises:

a phase detection circuit, coupled to one of the transition sampling circuits to receive a lock signal and a sampled transition data signal, and the center sampling circuit to receive a center sample signal, for generating an up-phase-adjust signal responsive to the lock signal indicating no lock, and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal, and for generating a down-phase-adjust signal responsive to the lock signal indicating no lock, and the transition data signal and center sample signal indicating the clock signal is lagging the data signal and generating a no-phase-adjust signal responsive to lock signal indicating a lock; and

a phase recommendation circuit, for comparing the up-phase-adjust signals, down-phase-adjust signals, and no-phase-adjust signals transmitted by the plurality of phase detection cells, to generate a phase recommendation signal.

17. A method for correcting skew between high-speed differential swing data signals and an associated clock signal comprising the steps of:

converting the clock signal into a full-swing clock signal;

generating a plurality of clock recovery signals from the full-swing clock signal;

converting the differential data signals into full-swing data signals;

oversampling the full-swing data signals responsive to the plurality of clock signals to produce oversampled data signals and lock signals;

generating skew control signals responsive to the oversampled data signals and lock signals; and

adjusting the skew of the data signals responsive to the skew control signals.

18. The method of claim 17 wherein the step of oversampling further comprises:

sampling transitions between two adjacent serial bits of data;

generating a lock signal and a sampled transition data signal responsive to the sampled transitions;

sampling a center point of each serial bit of data;

generating a center sample signal responsive to the sample; and

the step of generating skew control signals further comprising generating skew control signals responsive to the center sample signals, lock signals, and sampled transition data signals.

19. The method of claim 17 wherein the step of oversampling further comprises:

generating a high threshold signal, a low threshold signal, and a middle threshold signal having a voltage equal to an ideal logic threshold of a full swing data signal;

comparing the voltage of the sampled center point of each serial bit of data to the middle threshold to generate a current skew signal and a next skew signal, wherein the skew signal is high responsive to the voltage of the sampled point exceeding the middle threshold signal; and

comparing the voltage of the sampled transition point to the middle transition for generating a lock signal responsive to the sampled voltage being equal to the voltage of the middle threshold signal, and for generating a high signal responsive to the sampled voltage exceeding the high threshold signal, and for generating a low signal responsive to the sampled voltage being less than the low threshold signal.

20. The method of claim 17 wherein the step of generating skew control signals further comprises:

generating an up-phase-adjust signal responsive to the lock signal indicating no lock and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal;

generating a down-phase-adjust signal responsive to the lock signal indicating no lock and the transition data signal and center sample signal indicating the clock signal is lagging the data signal;

generating a no-phase-adjust signal responsive to the lock signal indicating a lock; and

comparing the plurality of up-phase-adjust signals, down-phase-adjust signals, and no-phase-adjust signals to generate a skew control signal.

21. A method for correcting skew between low-voltage differential swing (LVDS) data signals and an LVDS clock signal comprising the steps of:

converting the LVDS clock signal into a full-swing clock signal;

generating a plurality of clock recovery signals from the full-swing clock signal;

converting LVDS data signals into full-swing data signals;

oversampling the full-swing data signals responsive to the plurality of clock signals to produce oversampled data signals and lock signals;

generating skew control signals responsive to the oversampled data signals and lock signals; and

adjusting the skew of the data signals responsive to the skew control signals.

22. The method of claim 21 wherein the step of oversampling further comprises:

sampling transitions between two adjacent serial bits of data;

generating a lock signal and a sampled transition data signal responsive to the sampled transitions;

sampling a center point of each serial bit of data;

generating a center sample signal responsive to the sample; and

the step of generating skew control signals further comprising generating skew control signals responsive to the center sample signals, lock signals, and sampled transition data signals.

23. The method of claim 21 wherein the step of oversampling further comprises:

generating a high threshold signal, a low threshold signal, a middle threshold signal having a voltage equal to an ideal logic threshold of a full swing data signal;

comparing the voltage of the sampled center point of each serial bit of data to the high threshold to generate a current skew signal and to the low threshold to generate a next skew signal, wherein the skew signal is high responsive to the voltage of the sampled point exceeding the middle threshold signal and low responsive to the voltage of the sampled point being less than the middle threshold signal; and

comparing the voltage of the sampled transition point to the middle transition for generating a lock signal responsive to the sampled voltage being equal to the voltage of the middle threshold signal, and for generating a high signal responsive to the sampled voltage exceeding the high threshold signal, and for generating a low signal responsive to the sampled voltage being less than the low threshold signal.

24. The method of claim 21 wherein the step of generating skew control signals further comprises:

generating an up-phase-adjust signal responsive to the lock signal indicating no lock and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal;

generating a down-phase-adjust signal responsive to the lock signal indicating no lock and the transition data signal and center sample signal indicating the clock signal is lagging the data signal;

generating a no-phase-adjust signal responsive to the lock signal indicating a lock; and

comparing the plurality of up-phase-adjust signals, down-phase-adjust signals, and no-phase-adjust signals to generate a skew control signal.

25. A method for correcting skew between a high-speed data signal and an associated clock signal comprising the steps of:

generating a plurality of clock recovery signals from the clock signal;

oversampling the data signal responsive to the plurality of clock signals to produce an oversampled data signal and a lock signal;

generating the skew control signal responsive to the oversampled data signal and the lock signal; and

adjusting the skew of the data signal responsive to the skew control signal.

26. The method of claim 25 wherein the step of oversampling further comprises:

sampling transitions between two adjacent serial bits of data;

generating a lock signal and a sampled transition data signal responsive to the sampled transitions;

sampling a center point of each serial bit of data;

generating a center sample signal responsive to the sample; and

the step of generating a skew control signal further comprising generating a skew control signal responsive to the center sample signal, lock signal, and sampled transition data signal.

27. The method of claim 26 wherein the step of generating skew control signals further comprises:

generating an up-phase-adjust signal responsive to the lock signal indicating no lock and the sample transition data signal and center sample signal indicating the data signal is lagging the clock signal;

generating a down-phase-shift signal responsive to the lock signal indicating no lock and the transition data signal and center sample signal indicating the clock signal is lagging the data signal;

generating a no-phase-adjust signal responsive to the lock signal indicating a lock; and

comparing the up-phase-adjust signal, down-phase-adjust signal, and no-phase-adjust signal to generate a skew control signal.