Method and system for flexible control of BIST registers based upon on-chip events

• US 6,374,370 B1
• Filed: 10/30/1998
• Issued: 04/16/2002
• Est. Priority Date: 10/30/1998
• Status: Expired due to Fees

• Current Assignee: Eli Lilly and Company, Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Fleischman, Jay, Bockhaus, John W
• Primary Examiner(s): Baderman, Scott T.
• Application Number:
  US09/183,173
• Time in Patent Office: 1,264 Days
• Field of Search: 714/39, 714/30, 714/28, 714/29, 714/45, 714/732-733, 714/47, 703/28
• US Class Current: 714/39
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence

Abstract

A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed. The debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprcessor, such as multiple-input-shift-registers and first-in-first-out devices, that facilitate in the monitoring and debugging of the microprocessor. The signature and recording elements may or may not be contained within the one or more BIST engines and may or may not be used in conjunction with the memory arrays or BIST engine(s) of the microprocessor.

Claims

1. A method of debugging and monitoring the performance of a microprocessor having a built-in-self-test (BIST) engine, comprising the steps of:

defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor;

defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action;

executing instructions on said microprocessor until said event occurs; and

in response to said event occurring, controlling one or more monitor-and-debug elements of the microprocessor within the BIST engine with the control information to perform one or more monitor or debug operations.

2. The method of claim 1, wherein the one or more monitor or debug operations include performing a signature analysis operation on a plurality of signals by one or more signature analysis elements of the microprocessor that are controlled by the control information.

3. The method of claim 2, wherein the plurality of signals are a plurality of memory operation signals to or from one or more memory elements of the microprocessor.

4. The method of claim 2, wherein the one or more signature analysis elements are contained within one or more built-in-self-test (BIST) engines of the microprocessor.

5. The method of claim 4, wherein the control information controls one or more control bits of a main control register of each BIST engine of the one or more BIST engines that controls operation of the one or more signature analysis elements contained within the one or more BIST engines.

6. The method of claim 2, wherein the one or more signature analysis elements are one or more multiple-input-shift-registers of the microprocessor.

7. The method of claim 1, wherein the one or more monitor or debug operations include recording a plurality of signals by one or more recording elements of the microprocessor that are controlled by the control information.

8. The method of claim 7, wherein the plurality of signals are a plurality of memory operation signals to or from one or more memory elements of the microprocessor.

9. The method of claim 7, wherein the one or more recording elements are contained within one or more built-in-self-test (BIST) engines of the microprocessor.

10. The method of claim 9, wherein the control information controls one or more control bits of a main control register of each BIST engine of the one or more BIST engines that controls operation of the one or more recording elements contained within the one or more BIST engines.

11. The method of claim 7, wherein the one or more recording elements are one or more first-in-first-out (FIFO) devices of the microprocessor.

12. A method of debugging and monitoring the performance of a microprocessor, comprising the steps of:

defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor;

defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action;

executing instructions on said microprocessor until said event occurs; and

in response to said event occurring, controlling one or more signature analysis elements of the microprocessor with the control information to perform signature analysis on a plurality of signals.

13. The method of claim 12, wherein the one or more signature analysis elements are one or more multiple-input-shift-registers of the microprocessor.

14. The method of claim 12, wherein the one or more signature analysis elements are contained within one or more built-in-self-test (BIST) engines of the microprocessor.

15. The method of claim 14, wherein the control information controls one or more control bits of a main control register of each BIST engine of the one or more BIST engines that controls operation of the one or more signature analysis elements contained within the one or more BIST engines.

16. The method of claim 12, wherein the plurality of signals are a plurality of memory operation signals to or from one or more memory elements of the microprocessor.

17. A method of debugging and monitoring the performance of a microprocessor, comprising the steps of:

defining an event by configuring an on-chip state machine to detect when a combination of state machine inputs is asserted, said combination of state machine inputs corresponding to said event, wherein said event may occur at any time during operation of the microprocessor and wherein the combination of state machine inputs may be asserted at any place on the microprocessor;

defining an action to be taken when said event occurs by configuring said on-chip state machine to drive control information onto a state machine output bus when said event occurs, said control information corresponding to said action;

executing instructions on said microprocessor until said event occurs; and

in response to said event occurring, controlling one or more recording elements of the microprocessor with the control information to record a plurality of signals.

18. The method of claim 17, wherein the plurality of signals are a plurality of memory operation signals to or from one or more memory elements of the microprocessor.

19. The method of claim 17, wherein the one or more recording elements are contained within one or more built-in-self-test (BIST) engines of the microprocessor.

20. The method of claim 19, wherein the control information controls one or more control bits of a main control register of each BIST engine of the one or more BIST engines that controls operation of the one or more recording elements contained within the one or more BIST engines.

21. The method of claim 17, wherein the one or more recording elements are one or more first-in-first-out (FIFO) devices of the microprocessor.

22. Apparatus for debugging and monitoring the performance of a microprocessor, comprising:

one or more memory arrays of the microprocessor;

a debug block of the microprocessor coupled to the memory arrays that drives control information onto a state machine output bus in response to an event, wherein said event may occur at any time during operation of the microprocessor; and

one or more built-in-self-test (BIST) engines of the microprocessor coupled to the debug block and the one or more memory arrays,

wherein in response to the event occurring, the control information controls one or more monitor-and-debug elements of the one or more BIST engines to perform one or more monitor or debug operations.

23. The apparatus of claim 22, wherein the one or more monitor or debug operations include performing a signature analysis operation on a plurality of signals and the control information controls one or more signature analysis elements of the one or more BIST engines to perform signature analysis on the plurality of signals.

24. The apparatus of claim 23, wherein the plurality of signals are a plurality of memory operation signals to or from the one or more memory arrays.

25. The apparatus of claim 23, wherein each BIST engine of the one or more BIST engines comprises:

a main control block;

one or more programmable address generation blocks controlled by the main control block to selectively provide address information to one or more on-chip memory arrays, comprising;

an address local control block having an address control register; and

one or more address-data blocks having a plurality of address-data registers controlled by the address control register to provide or monitor address information from either the one or more address generation blocks or a CPU of an integrated circuit device to one or more on-chip memory arrays to which the one or more address-data blocks are coupled in accordance with instructions programmed into the address control register; and

one or more programmable data generation blocks controlled by the main control block to selectively provide and receive data information to and from the one or more on-chip memory arrays, comprising;

a data local control block having a data control register; and

one or more data—

data blocks having a plurality of data—

data registers controlled by the data control register of the data local control block to provide or monitor data information from either the one or more data generation blocks or the CPU of the integrated circuit device to the one or more on-chip memory arrays to which the one or more data—

data blocks are coupled in accordance with instructions programmed into the data control register and to receive information from the one or more on-chip memory arrays,

wherein the main control block is programmed by programming a main control register of the main control block to coordinate when the one or more address generation blocks and the one or more data generation blocks execute their programming; and

wherein the control information controls one or more control bits of the main control register of each BIST engine to control operation of the one or more signature analysis elements.

26. The apparatus of claim 25, wherein the one or more signature analysis elements are one or more of the one or more address-data registers or of the one or more data—

data registers.

27. The apparatus of claim 26, wherein the one or more signature analysis elements are multiple-input-shift-registers.

28. The apparatus of claim 23, wherein the one or more signature analysis elements are one or more multiple-input-shift-registers of the microprocessor.

29. The apparatus of claim 22, wherein the one or more monitor or debug operations include recording a plurality of signals by one or more recording elements of the one or more BIST engines that are controlled by the control information.

30. The apparatus of claim 29, wherein the plurality of signals are a plurality of memory operation signals to or from one or more memory elements of the microprocessor.

31. The apparatus of claim 29, wherein each BIST engine of the one or more BIST engines comprises:

a main control block;

one or more programmable address generation blocks controlled by the main control block to selectively provide address information to one or more on-chip memory arrays, comprising;

an address local control block having an address control register; and

one or more address-data blocks having a plurality of address-data registers controlled by the address control register to provide or monitor address information from either the one or more address generation blocks or a CPU of an integrated circuit device to one or more on-chip memory arrays to which the one or more address-data blocks are coupled in accordance with instructions programmed into the address control register; and

one or more programmable data generation blocks controlled by the main control block to selectively provide and receive data information to and from the one or more on-chip memory arrays, comprising;

a data local control block having a data control register; and

one or more data—

data blocks having a plurality of data—

data registers controlled by the data control register of the data local control block to provide or monitor data information from either the one or more data generation blocks or the CPU of the integrated circuit device to the one or more on-chip memory arrays to which the one or more data—

data blocks are coupled in accordance with instructions programmed into the data control register and to receive information from the one or more on-chip memory arrays,

wherein the main control block is programmed by programming a main control register of the main control block to coordinate when the one or more address generation blocks and the one or more data generation blocks execute their programming; and

wherein the control information controls the main control register of each BIST engine to control operation of the one or more recording elements.

32. The apparatus of claim 31, wherein the one or more recording elements are one or more of the one or more address-data registers or one or more of the one or more data—

data registers.

33. The apparatus of claim 32, wherein the one or more recording elements are first-in-first-out (FIFO) registers.

34. The apparatus of claim 29, wherein the one or more recording elements are first-in-first-out (FIFO) registers of the microprocessor.

35. The apparatus of claim 22, wherein the debug block comprises:

an on-chip state machine capable of being configured to detect when a combination of state machine inputs is asserted and to drive the control information onto a state machine output bus when said combination is detected;

a plurality of signal sources having their outputs coupled to said state machine inputs, the outputs of said plural signal sources representing debug related and performance-related information about said microprocessor; and

at least one on-chip output device coupled to said state machine output bus, said at least one on-chip output device for effecting, responsive to said control information, an action that will facilitate debugging and performance monitoring in said microprocessor.