Error processing circuit for a receiving location of a data transmission system

• US 6,374,374 B1
• Filed: 06/11/1999
• Issued: 04/16/2002
• Est. Priority Date: 06/12/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics GmbH (STMicroelectronics NV)
• Original Assignee: STMicroelectronics GmbH (STMicroelectronics NV)
• Inventors: Heinrich, Peter
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US09/330,475
• Time in Patent Office: 1,040 Days
• Field of Search: 714/752, 714/709, 714/712, 714/714, 714/715, 714/819, 714/820, 714/821, 714/56, 714/43, 370/242, 370/244, 370/247
• US Class Current: 714/709
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value. A line condition detector circuit detects error-free line conditions, line errors of the first line, and line errors of the second line, depending on the decoder output signals, and changeover control signals can be delivered to a changeover switch to deliver properly decoded data, depending on the particular detection result.

Claims

1. An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, the system including a number of receiving locations connected via a double-line bus having a first line and a second line,

a first logic value of the binary data represented by a high potential value on the first line and a low potential value on the second line, and a second logic value of the binary data represented by a low potential value on the first line and a high potential value on the second line;

each pulse sequence having no more than a predetermined number of equal data bits in succession;

the circuit comprising;

a data output;

a decoder having three decoder outputs, of which a first decoder output is associated with the first and second lines the decoder configured to deliver a first decoder output signal dependent on the difference between the potential values of both lines, and a second decoder output associated with the first line and configured to deliver a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line to deliver a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value, the first mean potential value and the second mean potential value each lying between the high potential value and the low potential value, and in an error-free case and upon occurrence of line errors of a first error group with a line error on one of the two lines, at least the first decoder output delivers properly decoded data, and upon occurrence of a second error group with a line error on one of the two lines, only the decoder output associated with the error-free other line still delivers properly decoded data;

a line condition detector circuit, by means of which error-free line conditions as well as line errors of the first line and line errors of the second line can be detected depending on the decoder output signals, and changeover control signals can be delivered depending on the particular detection result; and

a controllable changeover switch by means of which the data output, upon detection of line conditions in which only the second or third decoder output delivers properly decoded data, is connected to this decoder output and otherwise to the first decoder output.

2. The error processing circuit of claim 1,

wherein the line condition detector circuit comprises:

a first logic circuit linking the first decoder output signal and the second decoder output signal and delivering a first logic signal;

a second logic circuit linking the first decoder output signal and the third decoder output signal and delivering a second logic signal;

a first time measuring circuit measuring the first logic signal and a second time measuring circuit measuring the second logic signal, by means of which a time measurement of logic signal values of the first and second logic signals, respectively, which may mean a line error, is carried out and a first and second line error signal, respectively, is generated when such a logic signal value, as of occurrence thereof, has a longer duration than a duration corresponding to the predetermined number of equal data bits; and

a third logic circuit linking the two line error signals, said third logic circuit configured to link the two line error signals and to provide the changeover control signal.

3. The error processing circuit of claim 2 wherein the first and second logic circuits each comprise a NOR element having a first input, a second input, and an output, the first input connected to the first decoder output, and the second input thereof being connected to the second and third decoder outputs, respectively.

4. The error processing circuit of claim 3,

wherein the first and second time measuring circuits each comprise a counter having a counting release/resetting input, a counting clock input, and a counter output, and the counting release/resetting inputs being connected to the output of the first and second logic circuits, respectively, the clock signal inputs thereof being each connected to a counting clock pulse source, and the counter outputs being connected to a first and second input, respectively, of the third logic circuit.

5. The error processing circuit of claim 4, wherein the third logic circuit comprises a third NOR element having a first input, a second input, and an output, and with an AND element having an inverting input, an non-inverting input, and an output, the first input of the third NOR element and the inverting input of the AND element are connected to the counter output of the first counter, and the second input of the third NOR element and the non-inverting input of the AND element are connected to the counter output of the second counter, the counter output of the first counter, the output of the third NOR element and the output of the AND element constitute a first, a second, and a third changeover control signal output, respectively, at which first, second and third changeover control signals, respectively, are available.

6. The error processing circuit of claim 5,

wherein the controllable changeover switch comprises a multiplexer having a first multiplexer input connected to the first decoder output, a second multiplexer input connected to the second decoder output, and a third multiplexer input connected to the third decoder output, a multiplexer output connected to the data output, and a first changeover control input connected to the first changeover control signal output, a second changeover control input connected to the second changeover control signal output, and a third changeover control input connected to the third changeover control output, with the data output, depending on whether a potential value to be rated as changeover control signal occurs at the first, second or third changeover control input, establishing a connection to the third, first and second comparator output, respectively.

7. The error processing circuit of claim 1, wherein the decoder comprises a first comparator, a second comparator and a third comparator, each having a first comparator input, a second comparator input, and a comparator output, the first and second inputs of the first comparator being connected to the first and second lines, respectively, the first comparator input of the second comparator being connected to the first line, the second comparator input of the third comparator being connected to the second line, and the second comparator input of the second comparator and the first comparator input of the third comparator being each connected to a reference voltage source delivering the respectively associated mean potential value, and the comparator output of the first comparator constituting the first decoder output, the comparator output of the second comparator constituting the second decoder output, and the comparator output of the third comparator constituting the third decoder output.

8. An error detection circuit for a double-line bus having a first line and a second line, the circuit comprising:

a decoder coupled to the first and second lines and configured to detect the condition of first and second signals on the first and second lines, respectively, and to output a decoder output signal corresponding to the condition; and

a line condition detector circuit coupled to the decoder and configured to receive the decoder output signal, the line condition detector circuit including logic circuits to determine which of the first and second lines is error-free and a switch circuit to couple the error-free line to an output.

9. The circuit of claim 8 wherein the decoder comprises a first comparator having a first input coupled to the first line, a second input to a first mean value voltage source, and a first decoder signal output;

a second comparator having a first input coupled to the first line, a second input coupled to the second line, and a second decoder signal output; and

a third comparator having a first input coupled to the second line, a second input coupled to a second mean value voltage source, and a third decoder signal output, the first and second mean value voltage sources having a value between the lowest potential value and the highest potential value of the first and second signals.

10. The circuit of claim 9 wherein the line condition detector circuit comprises a first logic circuit having a first input coupled to the first decoder signal output, a second input coupled to the second decoder signal output, and a first logic signal output;

a second logic circuit having a first input coupled to the third decoder signal output, a second input coupled to the second decoder signal output, and a second logic signal output;

a first timer circuit having a first input coupled to the first logic signal output, a second input coupled to a clock signal, and a first timer output; and

a second timer circuit having a first input coupled to the second logic signal output, a second input coupled to the clock signal, and a second timer output.

11. The circuit of claim 10 wherein the first and second logic circuits comprise NOR elements.

12. The circuit of claim 10 wherein the line condition detector circuit further comprises a third logic circuit having a first input coupled to the first timer output, a second input coupled to the second timer output, and a third logic signal output;

a fourth logic circuit having a first input coupled to the first timer output, a second input coupled to the second timer output, and a fourth logic signal output.

13. The circuit of claim 12 wherein the switch circuit comprises a multiplexer having a first input coupled to the first decoder signal output, a second input coupled to the second decoder signal output, a third input coupled to the third decoder signal output, a fourth input coupled to the first timer output, a fifth input coupled to the third logic signal output, and a sixth input coupled to the fourth logic signal output, and a multiplexer output coupled to the output of the switch circuit, the multiplexer being configured to select one of the first, second, and third decoder signal outputs in response to the first timer output, the third logic signal output, and the fourth logic signal output that is rendering a decoding signal.

14. The circuit of claim 13 wherein the third logic circuit comprises an AND gate and the fourth logic circuit comprises a NOR gate.

15. A method of error detection on a data transmission system having a dual-line bus, the bus having a first line and a second line for conducting first and second signals, respectively, the method comprising:

comparing the first signal on the first line to a first reference voltage and generating a first decoder signal;

comparing the first signal and the second signal and generating a second decoder signal;

comparing the second signal on the second line to a second reference voltage and generating a third decoder signal;

detecting line faults on the first and second lines from the first, second, and third decoder signals; and

selecting one of the first and second lines that does not have a line fault.

16. The method of claim 15 wherein detecting line faults comprises monitoring the first line and the second line for successive bit sequences in the first signal and in the second signal that exceed an associated predetermined period of time.

17. The method of claim 16 wherein monitoring the first and second lines comprises monitoring for stuck-at-one and stuck-at-zero faults.

18. The method of claim 16 wherein monitoring comprises NOR′

g the first and second decoder signals and generating a first logic signal;

NOR′

g the second and third decoder signals and generating a second logic signal;

timing the first logic signal and generating a first timing signal; and

timing the second logic signal and generating a second timing signal.

19. The method of claim 18 wherein monitoring further comprises AND′

g the first and second timing signals to generate a third logic signal, and NOR'"'"'g the first and second timing signals to generate a fourth logic signal.

20. The method of claim 19 wherein selecting one of the first lines comprises multiplexing the first decoding signal, the second decoding signal, the third decoding signal, the first timing signal, the third logic signal, and the fourth logic signal.