Annealed porous silicon with epitaxial layer for SOI

• US 6,376,285 B1
• Filed: 05/20/1999
• Issued: 04/23/2002
• Est. Priority Date: 05/28/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swanson, Leland S., Joyner, Keith A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Berry, Reneé R.
• Application Number:
  US09/314,983
• Time in Patent Office: 1,069 Days
• Field of Search: 438/150, 438/149, 438/453, 438/454, 438/749, 438/750, 438/751, 205/656, 205/660, 205/662, 205/674
• US Class Current: 438/149
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/3167 of anodic oxidation
• CPC Class Codes: H01L 21/7627 Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques

Abstract

An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.

Claims

1. A method of forming a silicon-on-insulator substrate, comprising the steps of:

(a.) anodically oxidizing a silicon wafer to produce a layer of porous silicon;

(b.) partially oxidizing said layer of porous silicon to form silicon oxide on surfaces of pores in the layer of porous silicon;

(c.) growing an epitaxial layer of silicon on said partially oxidized layer of porous silicon; and

(d.) annealing said wafer to form a continuous buried oxide from the silicon oxide in the layer of porous silicon, with substantially smooth interfaces.

2. The method of claim 1, wherein said step (d.) is performed at a temperature which is greater than 1250 degrees C. for a time which is greater than two hours.

3. The method of claim 1, wherein said layer of porous silicon is formed in a boron-doped region.

4. A fabrication method, comprising the steps of:

(a.) anodically oxidizing a silicon wafer to produce a layer of porous silicon;

(b.) partially oxidizing said layer of porous silicon;

(c.) etching said partially oxidized layer of porous silicon to remove the oxide of step (b.) from the top surface of said porous silicon;

(d.) growing an epitaxial layer of silicon on said partially oxidized layer of porous silicon;

(e.) covering said epitaxial layer with a capping layer which prevents oxidation of said epitaxial layer;

(f.) annealing said wafer to allow said partially oxidized layer of porous silicon to separate into distinct layers which include a buried oxide layer;

(g.) forming transistor structures in said epitaxial layer of silicon;

whereby said buried oxide layer provides insulation for said transistor structures.

5. The method of claim 4, wherein step (c.) uses HF and H2O to etch oxide from the top surface of said porous silicon.

6. The method of claim 4, wherein step (c.) uses a plasma etch to etch oxide from the top surface of said porous silicon.

7. The method of claim 4, wherein said capping layer comprises Si3N4, SiC, SiO2 or any combination of these.

8. The method of claim 4, wherein said step (f.) includes an oxidation