Method of semiconductor device fabrication

• US 6,376,314 B1
• Filed: 05/05/2000
• Issued: 04/23/2002
• Est. Priority Date: 11/07/1997
• Status: Expired due to Term

• Current Assignee: Zetex Plc (Diodes Incorporated)
• Original Assignee: Zetex Plc (Diodes Incorporated)
• Inventors: Jerred, Paul Antony
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/530,802
• Time in Patent Office: 718 Days
• Field of Search: 438/268, 438/270, 438/184, 438/302, 438/303, 438/639, 438/529, 438/525, 438/561, 438/527, 438/138
• US Class Current: 438/270
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of semiconductor device fabrication comprising forming at least the indentation in a surface of a semiconductor body. The indentation is partially filled with a filler material such that walls of the indentation are exposed above an upper surface of the filler material. First and second dopants are introduced through the exposed walls of the indentation and first and second doped regions formed. The first doped region extends into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material. The second doped region extends into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material. The first and second depths are different such that a region of predetermined thickness is defined adjacent the indentation between the first and second boundaries.

Claims

1. A method of semiconductor device fabrication comprising forming at least one indentation in a surface of a semiconductor body, partially filling the indentation with a filler material such that walls of the indentation are exposed above an upper surface of the filler material, and introducing and diffusing first and second dopants through the exposed walls of the indentation to form first and second doped regions, the first doped region extending into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material, and the second doped region extending into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material, the first and second depths being different such that a region of predetermined thickness is defined adjacent the indentation between the first and second boundaries.

2. A method according to claim 1, wherein the indentation is an elongate trench.

3. A method according to claim 1, wherein the step of partially filling the indentation with a filler material comprises filling completely the indentation with filler material, then etching the filler material part way into the indentation.

4. A method according to claim 1, wherein the filler material is polysilicon.

5. A method according to claim 1, wherein a layer of dielectric is formed upon surfaces of the indentation prior to the indentation being partially filled.

6. A method according to claim 5, wherein one or both of the dopants are introduced into the walls of the indentation through the dielectric layer.

7. A method according to claim 5, wherein the dielectric layer is at least partially removed from those surfaces of the indentation which are exposed above the partially filled portion of the indentation, prior to the introduction of one or both of the dopants.

8. A method according to claim 1, wherein at least one of the dopants is produced by an ionic source which is disposed at an angle to the indentation.

9. A method according to claim 1, wherein at least a portion of a previously defined masking layer substantially prevents one or both of the dopants from entering at least a portion of the surface of the semiconductor body.

10. A method according to claim 9, wherein the thickness and composition of the previously defined masking layer is such that it functions substantially as a barrier to the introduction of one of the dopants but is substantially penetrated by the other dopant.

11. A method according to claim 10, wherein the one dopant is introduced by ion implantation carried out at a relatively low energy and the other dopant is introduced by ion implantation carried out at a relatively high energy.

12. A method according to claim 1, wherein the first dopant is arranged to penetrate further into the side walls of the indentation than the second dopant.

13. A method according to claim 1, wherein the second dopant is arranged to penetrate further into the walls of the indentation than the first dopant.

14. A method according to claim 9, wherein at least a portion of the previously defined masking layer covering at least a portion of the surface of the semiconductor body is arranged such that it functions substantially as a barrier to the introduction of the one dopant, but is at least partially removed prior to introduction of the other dopant.

15. A method according to claim 1, wherein the first and second dopants are diffused simultaneously to form the first and second doped regions.

16. A method according to claim 1, wherein the semiconductor device is a MOSFET with gate regions provided by the filler material, body regions provided by the deeper of the first and second doped regions, and source regions provided by the shallower of the first and second doped regions.

17. A method according to claim 16, wherein the MOSFET is a n-channel (n-p-n) type structure.

18. A method according to claim 16, wherein the MOSFET is a p-channel (p-n-p) type structure.

19. A method according to claim 1, wherein the semiconductor body is formed on a further body of semiconductor which defines a drain region.

20. A method according to claim 19, wherein a further layer of opposite conductivity type to the further body of semiconductor is formed on a side of the further body of semiconductor remote from the surface of the semiconductor body.