Method of forming a trench DMOS having reduced threshold voltage

• US 6,376,315 B1
• Filed: 03/31/2000
• Issued: 04/23/2002
• Est. Priority Date: 03/31/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/540,856
• Time in Patent Office: 753 Days
• Field of Search: 438/270, 438/271, 438/272, 257/330
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696

Abstract

A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.

Claims

1. A method of manufacturing one or more trench DMOS transistors comprising:

providing a substrate of a first conductivity type, forming an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate;

forming a region of a second conductivity type within an upper portion of said epitaxial layer;

forming A plurality of trenches within said epitaxial layer, said trenches defining one or more body regions within said region of second conductivity type, forming a first insulating layer that lines said trenches;

providing a conductive region within said trenches adjacent to the first insulating layer lining said trenches;

removing a portion of said first insulating layer along at least upper sidewalls of said trenches such that portions of said body regions are exposed along said upper sidewalls;

oxidizing at least said exposed portions of said body regions to form an oxide layer, said oxidizing step resulting in regions of reduced majority carrier concentration within said body regions adjacent said oxide layer; and

forming a plurality of source regions of said first conductivity type within upper portions of said body regions adjacent said trenches, said source regions being adjacent said regions of reduced majority carrier concentration within said body regions.

2. The method of claim 1, wherein said substrate is a silicon substrate and said epitaxial layer is a silicon layer.

3. The method of claim 1, wherein the step of forming the region of second conductivity type includes implanting and diffusing a dopant into the epitaxial layer.

4. The method of claim 1, wherein the step of forming the trenches includes the step of forming a patterned masking layer over the epitaxial layer and etching said trenches through said masking layer.

5. The method of claim 1, wherein said first insulating layer is an oxide layer.

6. The method of claim 1, wherein the step of forming the first insulating layer comprises providing an oxide layer via dry oxidation.

7. The method of claim 1, wherein the step of removing a portion of the first insulating layer along at least upper sidewalls of the trenches is conducted via wet etch.

8. The method of claim 1, wherein the conductive region is a polycrystalline silicon region.

9. The method of claim 1, wherein the step of providing a conductive region within said trenches comprises depositing a layer of polycrystalline silicon and subsequently etching the polycrystalline silicon layer.

10. The method of claim 1, wherein the step of oxidizing at least the exposed upper sidewall portions of the body regions comprises dry oxidation at a temperature ranging frorn 900 to 1100°

C.

11. The method of claim 10, wherein the temperature ranges from 900 to 950°

C.

12. The method of claim 1, wherein the step of oxidizing at least the exposed upper sidewall portions of the body regions comprises oxidation in steam at a temperature ranging from 900 to 1100°

C.

13. The method of claim 12, wherein the temperature ranges from 900 to 950°

C.

14. The method of claim 1, wherein the step of forming the source regions includes the steps of forming a patterned masking layer and implanting and diffusing a dopant into the body regions.

15. The method of claim 1, wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity.

16. The method of claim 1, wherein said body region is doped with boron.

17. A method of manufacturing one or more trench DMOS transistors comprising:

providing an N-type silicon substrate forming an N-type silicon epitaxial layer over said substrate, said epitaxial layer having a tower doping concentration than said substrate;

forming a P-type region within an upper portion of said epitaxal layer, fording a plurality of trenches within said epitaxial layer, said trenches defining one or more P-body regions within said P-type region;

foxing a first oxide layer that lines said trenches;

providing a conductive region within said trenches adjacent the first oxide layer lining said trenches;

removing a portion of said first oxide layer along at least upper sidewalls of said trenches such that portions of said P-body regions are exposed along said upper sidewalls;

oxidizing at least said exposed portions of said P-body regions to form a second oxide layer, said oxidizing step resulting in regions of reduced P-type carrier concentration within said P-body regions adjacent said second oxide layer; and

forming a plurality of N-type source regions within upper portions of said P-body regions adjacent said trenches, said N-type source regions being adjacent said regions of reduced P-type carrier concentration within said P-body regions.

18. The method of claim 17, wherein the conductive region is a polycrystalline silicon region.

19. The method of claim 17, wherein the step of oxidizing at least the exposed upper sidewall portions of the P-body regions comprises dry oxidation at a temperature ranging from 900 to 1100°

C.

20. The method of claim 19, wherein the temperature ranges from 900 to 950°

C.

21. The method of claim 17, wherein the step of oxidizing at least the exposed upper sidewall portions of the P-body regions comprises wet oxidation in steam at a temperature ranging from 900 to 1100°

C.

22. The method of claim 21, wherein the temperature ranges from 900 to 950°

C.

23. The method of claim 17, wherein said P-body regions are doped with boron.

24. A Tnethod of modifying the majority carrier concentration in a body region within a trench D)MOS transistor comprising:

providing one or mote or more body regions adjacent one or more trenches, said one or more trenches being lined with a first insulating layer;

removing a portion of said first insulating layer along at least upper sidewalls of said trenches such that portions of said body regions are exposed along said upper sidewalls; and

oxidizing at least said exposed portions of said body regions, said oxidizing step resulting in regions of reduced majority carrier concentration within said body regions adjacent said oxide layer.