Vertical DRAM cell with robust gate-to-storage node isolation

• US 6,376,873 B1
• Filed: 04/07/1999
• Issued: 04/23/2002
• Est. Priority Date: 04/07/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hakey, Mark C., Kanarsky, Thomas S., Furukawa, Toshiharu, Horak, David V., Holmes, Steven J., Welser, Jeffrey J.
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US09/287,410
• Time in Patent Office: 1,112 Days
• Field of Search: 257/301, 257/302, 257/303, 257/304, 257/305, 257/905
• US Class Current: 257/301
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.

Claims

1. A dynamic random access memory device comprising:

a substrate having a trench formed therein, the trench having a lower portion, a top, a circumference and a side wall;

a signal storage node including a storage node conductor formed in the lower portion of the trench, a node dielectric, and a collar oxide disposed above the node dielectric, the storage node conductor isolated from the side wall by the node dielectric and by the collar oxide;

a buried strap coupled to the storage node conductor and contacting a portion of the side wall of the trench along a fragment of the trench circumference above the collar oxide;

a trench-top dielectric having a trench-top dielectric thickness formed upon the buried strap;

a signal transfer device including;

a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap,

a gate insulator having a gate insulator thickness formed on the trench side wall above the buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and

a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator; and

a trench insulator formed in the trench extending from the top of the trench down through a portion of the collar oxide and extending around the circumference of the trench exclusive of the fragment of the trench contacted by the buried strap.

2. A dynamic random access memory device according to claim 1 wherein the device has a signal storage node leakage current less than 10⁻

17 amperes.

3. A dynamic random access memory device comprising:

a substrate having a trench formed therein, the trench having a lower portion and a side wall;

a signal storage node including a storage node conductor formed in the lower portion of the trench, a node dielectric, and a collar oxide disposed above the node dielectric, the storage node conductor isolated from the side wall by the node dielectric and by the collar oxide;

a buried strap coupled to the storage node conductor and contacting a portion of the side wall of the trench above the collar oxide;

a trench-top dielectric having a trench-top dielectric thickness formed upon the buried strap; and

a signal transfer device including;

a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap,

a gate insulator having a gate insulator thickness formed on the trench side wall above the buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and

a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator;

wherein a ratio of the trench-top dielectric thickness to the gate insulator thickness ranges between 3;

1 and 12;

1.

4. A dynamic random access memory device comprising:

a substrate having a trench formed therein, the trench having a lower portion and a side wall;

a signal storage node including a storage node conductor formed in the lower portion of the trench, a node dielectric, and a collar oxide disposed above the node dielectric, the storage node conductor isolated from the side wall by the node dielectric and by the collar oxide;

a buried strap coupled to the storage node conductor and contacting a portion of the side wall of the trench above the collar oxide;

trench-top dielectric having a trench-top dielectric thickness that ranges between 20 nm and 100 nm formed upon the buried strap; and

a signal transfer device including;

a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap,

a gate insulator having a gate insulator thickness formed on the trench side wall above the buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and

a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.

5. A dynamic random access memory device comprising:

a substrate having a trench formed therein, the trench having a lower portion, a circumference and a side wall;

a signal storage node including a storage node conductor formed in the lower portion of the trench, a node dielectric, and a collar oxide disposed above the node dielectric, the storage node conductor isolated from the side wall by the node dielectric and by the collar oxide;

a buried strap coupled to the storage node conductor and contacting a portion of the side wall of the trench along a fragment of the trench circumference and above the collar oxide;

a trench-top dielectric having a trench-top dielectric thickness formed upon the buried strap; and

a signal transfer device including;

a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap,

a gate insulator having a gate insulator thickness formed on the trench side wall above the buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and

a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.

6. A dynamic random access memory device according to claim 5 wherein the trench has a top and the device further comprises a trench insulator formed in the trench extending from the top of the trench down through a portion of the collar oxide and extending around the circumference of the trench exclusive of the fragment of the trench contacted by the buried strap.

7. A dynamic random access memory device according to claim 6 wherein a ratio of the trench-top dielectric thickness to the gate insulator thickness ranges between 3:

1 and 12;

1.