NAND-type flash memory devices and methods of fabricating the same

• US 6,376,876 B1
• Filed: 10/04/2000
• Issued: 04/23/2002
• Est. Priority Date: 01/17/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hur, Sung-Hoi, Park, Kyu-Charn, Shin, Kwang-Shik, Oh, Heung-Kwun
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/678,917
• Time in Patent Office: 566 Days
• Field of Search: 257/315, 257/318, 257/319
• US Class Current: 257/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Claims

1. A NAND-type flash memory device, comprising:

a plurality of isolation layers formed at predetermined regions of a semiconductor substrate, the plurality of isolation layers running parallel with each other;

a string selection line pattern and a ground selection line pattern crossing over active regions between the plurality of isolation layers, the string selection line pattern and the ground selection line pattern running parallel with each other;

a plurality of word line patterns disposed between the string selection line pattern and the ground selection line pattern;

source regions formed at the active regions adjacent to the ground selection line patterns, the source regions being located opposite the string selection line pattern;

drain regions formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern; and

a common source line disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern, being electrically connected to the source regions, and being in direct contact with the isolation layers.

2. The NAND-type flash memory device of claim 1, further comprising a plurality of bit lines crossing over the plurality of word line patterns and the common source line patterns, the plurality of bit lines being electrically connected to the respective drain regions.

3. The NAND-type flash memory device of claim 2, further comprising a drain contact plug interposed between the drain region and the bit line.

4. The NAND-type flash memory device of claim 2, further comprising first and second interlayer insulating layers sequentially stacked between the plurality of word line patterns and the plurality of bit lines.

5. The NAND-type flash memory device of claim 4, wherein the top surface level of the common source line is even with that of the first insulating layer.

6. The NAND-type flash memory device of claim 4, wherein the top surface level of the common source line is lower than that of the first insulating layer.

7. The NAND-type flash memory device of claim 2, further comprising a second interlayer insulating layer interposed between the common source line and the plurality of bit lines.

8. The NAND-type flash memory device of claim 1, wherein the common source line comprises a doped polysilicon layer and a metal silicide layer which are sequentially stacked.

9. A NAND-type flash memory device, comprising:

a plurality of isolation layers formed at predetermined regions of a semiconductor substrate, the plurality of isolation layers running parallel with each other;

a string selection line pattern and a ground selection line pattern crossing over active regions between the plurality of isolation layers, the string selection line pattern and the ground selection line pattern running parallel with each other;

a plurality of word line patterns disposed between the string selection line pattern and the ground selection line pattern;

source regions formed at the active regions adjacent to the ground selection line patterns, the source regions being located opposite the string selection line pattern;

drain regions formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern;

a common source line disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern and being electrically connected to the source regions;

a plurality of bit lines crossing over the plurality of word line patterns and the common source line, the plurality of bit lines being electrically connected to respective drain regions; and

first and second interlayer insulating layers sequentially stacked between the plurality of word line patterns and the plurality of bit lines;

wherein a top surface level of the common source line is even with a top surface level of the first insulating layer.

10. A NAND-type flash memory device, comprising:

a plurality of isolation layers formed at predetermined regions of a semiconductor substrate, the plurality of isolation layers running parallel with each other;

a string selection line pattern and a ground selection line pattern crossing over active regions between the plurality of isolation layers, the string selection line pattern and the ground selection line pattern running parallel with each other;

a plurality of word line patterns disposed between the string selection line pattern and the ground selection line pattern;

source regions formed at the active regions adjacent to the ground selection line patterns, the source regions being located opposite the string selection line pattern;

drain regions formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern;

a common source line disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern and being electrically connected to the source regions;

a plurality of bit lines crossing over the plurality of word line patterns and the common source line, the plurality of bit lines being electrically connected to respective drain regions; and

first and second interlayer insulating layers sequentially stacked between the plurality of word line patterns and the plurality of bit lines;

wherein a top surface level of the common source line is lower than a top surface level of the first insulating layer.