Semiconductor device and method of manufacturing the same

• US 6,376,888 B1
• Filed: 04/27/2000
• Issued: 04/23/2002
• Est. Priority Date: 04/30/1999
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Murakoshi, Atsushi, Suguro, Kyoichi, Iinuma, Toshihiko, Matsuo, Kouji, Tsunashima, Yoshitaka
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nhu, David
• Application Number:
  US09/559,356
• Time in Patent Office: 726 Days
• Field of Search: 257/288, 257/310, 257/401, 257/407, 257/412, 257/413, 257/510, 257/377, 257/742, 257/761, 257/763
• US Class Current: 257/407
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the metal-containing film constituting at least a part of the second gate electrode and in contact with the second gate insulating film.

Claims

1. A semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region,

wherein, said N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on said first gate insulating film;

said P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on said second gate insulating film;

each of said first and second gate electrodes includes at least one metal-containing film having a metallic property, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films having a metallic property; and

a work function of the metal-containing film having a metallic property constituting at least a part of said first gate electrode and in contact with said first gate insulating film is smaller than a work function of the metal-containing film having a metallic property constituting at least a part of said second gate electrode and in contact with said second gate insulating film.

2. The semiconductor device according to claim 1, wherein the metal-containing film constituting at least a part of said first gate electrode is selected from the group consisting of a metal film and a metal compound film, and the metal-containing film constituting at least a part of said second gate electrode is selected from the group consisting of a metal film and a metal compound film.

3. The semiconductor device according to claim 2, wherein said metal compound film is selected from the group consisting of a metal silicide film and a metal nitride film.

4. The semiconductor device according to claim 1, wherein the metal-containing film, which is included in said laminate structure forming said first gate electrode and is in contact with said first gate insulating film, is formed along the bottom and side wall of said first concave portion.

5. The semiconductor device according to claim 1, wherein the metal-containing film, which is included in said laminate structure forming said second gate electrode and is in contact with said second gate insulating film, is formed along the bottom and side wall of said second concave portion.

6. The semiconductor device according to claim 1, wherein the metal-containing film, which is included in said laminate structure forming said first gate electrode and is in contact with said first gate insulating film, is thicker on a bottom of said first concave portion than on a side wall of the first concave portion.

7. The semiconductor device according to claim 1, wherein the metal-containing film, which is included in said laminate structure forming said second gate electrode and is in contact with said second gate insulating film, is thicker on a bottom of said second concave portion than on a side wall of the second concave portion.

8. The semiconductor device according to claim 1, wherein said first gate electrode is formed of a laminate structure consisting of a hafnium nitride film and a cobalt film, said second gate electrode is formed of a cobalt film, and each of said first and second gate insulating films is formed of a hafnium oxide film.