Static clock pulse generator, spatial light modulator and display
First Claim
Patent Images
1. A static clock pulse generator comprising a clock input and N stages, wherein each ith one of the stages comprises a reset-set flip-flop having a set input for receiving a set signal from a gating circuit of the (i−
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from at least one clock signal input of the gating circuit connected to the clock input to an output of the gating circuit when the flip-flop is set, where 1<
i≦
(N−
a), wherein the or each clock signal input of each gating circuit is connected exclusively, within the gating circuit, to a terminal of the main conduction path of a pass gate of the gating circuit.
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Abstract
A static clock pulse generator comprises a plurality of stages, each of which comprises a reset-set flip-flop and a gating circuit. Complementary outputs of the flip-flop control the gating circuit for supplying clock pulses from a clock input to the output of the stage. When the gating circuit is switched off, it holds the output at a default level. The flip-flop has a set input which receives the output from the preceding stage and a reset input which receives the output from the following stage.
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Citations
38 Claims
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1. A static clock pulse generator comprising a clock input and N stages, wherein each ith one of the stages comprises a reset-set flip-flop having a set input for receiving a set signal from a gating circuit of the (i−
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from at least one clock signal input of the gating circuit connected to the clock input to an output of the gating circuit when the flip-flop is set, where 1<
i≦
(N−
a), wherein the or each clock signal input of each gating circuit is connected exclusively, within the gating circuit, to a terminal of the main conduction path of a pass gate of the gating circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from at least one clock signal input of the gating circuit connected to the clock input to an output of the gating circuit when the flip-flop is set, where 1<
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35. A generator comprising a clock input and N stages, wherein each ith one of the stages includes a reset-set flip-flop having a set input for receiving a set signal from a gating circuit output of the (i−
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from the clock input to an output of the gating circuit when the flip-flop is set, where 1<
i≦
(N−
a), wherein the or each clock signal input of each gating circuit is connected exclusively, within the gating circuit, to a terminal of the main conduction path of a pass gate of the gating circuit, and further comprising a CMOS integrated circuit.
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from the clock input to an output of the gating circuit when the flip-flop is set, where 1<
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36. A spatial light modulator, comprising a static clock pulse generator including a clock input and N stages, wherein each ith one of the stages includes a reset-set flip-flop having a set input for receiving a set signal from a gating circuit output of the (i−
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from the clock input to an output of the gating circuit-when the flip-flop is set, where 1<
i≦
(N−
a), wherein the or each clock signal input of each gating circuit is connected exclusively, within the gating circuit, to a terminal of the main conduction path of a pass gate of the gating circuit. - View Dependent Claims (37, 38)
- 1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from the clock input to an output of the gating circuit-when the flip-flop is set, where 1<
Specification