Programmable relaxation oscillator
First Claim
1. An oscillator comprising:
- a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, the slope fixing circuit comprising a floating timing capacitor block that has an effective capacitance C and a current supply block that supplies a control current I, wherein the slope of the control signal is determined by the ratio of the control current to the effective capacitance (I/C), and wherein the timing capacitor block comprises a fixed timing capacitor C1 and at least one switchable timing capacitor C2 connected in parallel with C1;
a swing-fixing circuit that fixes the swing of the control signal; and
a switching block that generates an oscillator output signal, wherein the oscillator output signal has a frequency derived from the swing and the slope of the control signal.
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Accused Products
Abstract
An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C1 in parallel with a plurality of switchable timing capacitors C2 . . . CN to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage VREF and provides a fixed voltage swing VSW=VDD−VREF across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal. The frequency of the output signal is given by
48 Citations
40 Claims
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1. An oscillator comprising:
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a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, the slope fixing circuit comprising a floating timing capacitor block that has an effective capacitance C and a current supply block that supplies a control current I, wherein the slope of the control signal is determined by the ratio of the control current to the effective capacitance (I/C), and wherein the timing capacitor block comprises a fixed timing capacitor C1 and at least one switchable timing capacitor C2 connected in parallel with C1;
a swing-fixing circuit that fixes the swing of the control signal; and
a switching block that generates an oscillator output signal, wherein the oscillator output signal has a frequency derived from the swing and the slope of the control signal. - View Dependent Claims (2, 3, 4)
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5. An oscillator comprising:
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a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, the slope fixing circuit comprising a floating timing capacitor block that has an effective capacitance C and a current supply block that supplies a control current I, wherein the slope of the control signal is determined by the ratio of the control current to the effective capacitance (I/C);
a swing-fixing circuit that fixes a swing of the control signal, wherein the swing-fixing circuit comprises a replica cell that provides a fixed voltage swing VSW, and a variable resistance load that the voltage swing is applied across; and
a switching block that generates an output signal, wherein the output signal has a frequency derived from the swing and the slope of the control signal. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A relaxation oscillator integrated on a single semiconductor chip comprising:
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a voltage-to-current converter that generates a control current I from an input voltage;
a current-controlled oscillator that generates an oscillating output signal from the control current I and an internal control signal, the current-controlled oscillator comprising at least one timing capacitor having an effective capacitance C that fixes the slope of the control signal as I/C;
a pair of load transistors that fixes the voltage swing VSW of the control signal; and
a pair of switching transistors coupled between the at least one capacitor and the load transistors that generate the oscillating output signal based on the internal control signal; and
a replica cell that provides a reference voltage VREF to the load transistors to fix the voltage swing across the load transistors. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
at least one fixed timing capacitor C1 and at feast one switchable timing capacitor C2 are connected in parallel between the sources of the switching transistors;
the load transistors are a pair of p-channel CMOS transistors having their sources connected to a supply voltage VDD and their gates connected to the reference voltage VREF provided by the replica cell, such that the voltage swing across the load transistors is VSW=VDD−
VREF; and
the switching transistors are a pair of n-channel CMOS transistors having their gates cross-coupled to their drains.
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24. A relaxation oscillator as claimed in claim 23, wherein:
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a plurality of switchable timing capacitors C2 . . . CN are provided such that the effective capacitance C is programmable through the placement of selected ones of timing capacitors C2 . . . CN in parallel with fixed timing capacitor C1; and
a plurality of reference voltages VREF1 . . . VREFM are provided such that the voltage swing VSW is programmable through the selection of one of the reference voltages VREF1 . . . VREFM.
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25. A relaxation oscillator as claimed in claim 24, wherein:
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the switching transistors have an aspect ratio of approximately 48/0.35;
the load transistors have an aspect ratio of approximately 24/1.0; and
the supply voltage is approximately 2.5 volts.
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26. A relaxation oscillator as claimed in claim 18, wherein the replica cell comprises an operational amplifier that accepts the reference voltage VREF and regulates the load transistors of the current controlled oscillator to maintain the voltage swing VSW at a fixed value.
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27. A phase-locked loop comprising:
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a phase/frequency detector that compares a reference clock signal with an output clock signal and generates an appropriate charge pump control voltage;
a charge pump coupled to the phase/frequency detector that generates a loop filter control current from the charge pump control voltage;
a loop filter coupled to the charge pump that generates a loop filter voltage from the loop filter control current;
an oscillator coupled to the loop filter that comprises a slope-fixing circuit that receives the loop filter voltage and generates a control signal having a fixed slope;
a swing-fixing circuit that fixes the swing of the control signal; and
a switching block that generates the output clock signal, wherein the output clock signal has a frequency derived from the swing and slope of the control signal; and
a feedback circuit coupled between the oscillator and the phase/frequency detector that provides the output clock signal to the phase/frequency detector, wherein;
the slope-fixing circuit comprises at least one timing capacitor C1 that provides an effective capacitance C and a current supply that provides a control current I, and the slope of the control signal is I/C;
the swing-fixing circuit comprises a pair of load transistors and a replica cell that fixes the voltage swing VSW across the load transistors; and
the switching block comprises a pair of switching transistors coupled between the at least one timing capacitor C1 and the load transistors to produce an oscillating output signal. - View Dependent Claims (28, 29, 30, 31)
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32. A method for generating an oscillating output signal VO comprising the following steps:
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(a) fixing a voltage swing VSW across a variable resistance load;
(b) fixing an effective timing capacitance C;
(c) providing a control current I;
(d) deriving a control signal slope from the control current I and the effective timing capacitance C;
(e) setting a control signal VC to an initial value based on the voltage swing VSW;
(f) outputting the signal VO at an initial level or at a switched level;
(g) decreasing the control signal VC along the control signal slope;
(h) continuing to output the signal VO at the current level as long as the change in the control voltage Δ
VC does not exceed a threshold voltage VT;
(i) switching the level of the output signal VO when Δ
VC exceeds the threshold voltage VT;
(j) repeating the method beginning with step (e) if the control current I has not changed; and
(k) repeating the method beginning with step (d) if the control current I has changed. - View Dependent Claims (33, 34, 35, 36, 37, 38)
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39. A method for programming the gain or sensitivity
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CV SW of an oscillator comprising the following steps; determining the desired gain KO;
coarse-tuning the oscillator by selecting an effective capacitance C to achieve the desired gain KO, wherein the oscillator is coarse-tuned by placing appropriate switchable timing capacitors C2 . . . CN in parallel with a fixed capacitor C1 to yield the desired effective capacitance C; and
fine-tuning the oscillator by selecting a voltage swing VSW across a variable resistance load to achieve the desired gain KO. - View Dependent Claims (40)
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Specification