System and method for providing a low power receiver design

• US 6,377,315 B1
• Filed: 11/12/1999
• Issued: 04/23/2002
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Carr, Frank
• Primary Examiner(s): Harvey, David E.
• Application Number:
  US09/439,102
• Time in Patent Office: 893 Days
• Field of Search: H04/N.710, H04/N.5455, 348/731, 348/726, 455/179.1, 455/196.1, 455/202, 455/188.1, 455/189.1, 455/190.1, 455/191.1, 455/205, 455/207, 455/208, 455/209, 725/151
• US Class Current: 348/726
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. An integrated receiver comprising:

a substrate providing a physical medium upon which a receiver circuit is disposed;

a first local oscillator;

a second local oscillator;

a mixer having its circuit elements disposed upon the substrate for converting a received signal to a first IF using the first local oscillator'"'"'s output to mix the received signal with;

a first buffer amplifier having its circuit elements disposed upon the substrate cascaded after the mixer;

an external first differential filter assembly coupled to the first buffer amplifier output for removing an image distortion from the first IF and removing unwanted channels;

a second buffer amplifier having its circuit elements disposed upon the substrate coupled to the external first differential filter assembly output;

a first I/Q mixer disposed upon the substrate for converting the first IF to a second IF I and Q signal and rejecting a first IF image distortion;

a polyphase circuit for combining the second IF I and Q signals into a second IF signal;

a third buffer amplifier having its circuit elements disposed upon the substrate and cascaded with the polyphase circuit; and

an external second differential filter assembly coupled to the third buffer amplifier output for removing an image distortion from the second IF and removing unwanted channels;

whereby frequency conversion, channel selectivity and image rejection are performed on the integrated circuit.

2. The integrated receiver of claim 1 additionally comprising an AGC circuit having its circuit elements disposed upon the substrate, cascaded after the external second differential filter assembly.

3. The integrated receiver of claim 1 additionally comprising a programable gain attenuator and LNA circuit having its circuit elements disposed upon the substrate, cascaded in front of the first mixer.

4. The integrated receiver of claim 1 wherein the substrate is silicon.

5. The integrated receiver of claim 1 wherein the substrate comprises devices fabricated according to standard CMOS processing.

6. The integrated receiver of claim 1 further comprising interconnection by differential signal transmission lines.

7. A receiver partially implemented on an integrated circuit chip, the receiver comprising:

means on the integrated circuit chip for receiving a plurality of channels of signals in a radio frequency telecast band;

a first mixer on the integrated circuit chip to which the plurality of channels of signals in a radio frequency telecast band are applied;

a first bandpass filter off the integrated circuit chip coupled onto the integrated circuit chip to an output of the first mixer, the first filter having a first pass band;

a first local oscillator (LO) on the integrated circuit chip coupled to the first mixer, the first LO having a variable frequency;

means on the integrated circuit chip for adjusting the first LO to select one of the plurality of channels and shift the selected one of the plurality of channels to the first pass band;

a second mixer on the integrated circuit chip to which the selected one of the plurality of channels is applied after the first mixer;

a second LO on the integrated circuit chip coupled to the second mixer, the second LO having a fixed frequency that shifts the selected one of the plurality of channels to an intermediate frequency;

means for demodulating the selected one of the plurality of channels; and

the receiving means, the first LO, and the second LO have differential outputs, the first and second mixers have differential inputs and outputs, and the first bandpass filter has a differential input and a differential output.

8. The receiver of claim 7, additionally comprising a second bandpass filter off the chip coupled onto the chip to the output of the second mixer, the second filter having a second passband, the second LO having a frequency that shifts the selected channel to the second pass band.

23. The integrated receiver of claim 7, wherein the plurality of channels of signals are a plurality of television channels.

24. The integrated receiver of claim 23, wherein the second mixer is and I/Q mixer.

9. A receiver, comprising:

a substrate providing a physical medium on which a portion of the receiver is disposed;

a first local oscillator;

a second local oscillator;

a first differential mixer, disposed on the substrate and coupled to the first local oscillator, that generates a first IF signal comprising a plurality of channels;

a first differential IF filter, coupled to the first mixer and external to the substrate, that produces a second IF signal by removing at least one of the plurality of channels from the first IF signal; and

a second differential mixer, disposed on the substrate and coupled to the second local oscillator, that generates a third IF signal from the second IF signal.

10. The receiver of claim 9, wherein the first differential IF filter is a surface acoustic wave (SAW) filter.

11. The receiver of claim 9, further comprising a second differential IF filter coupled to an output of the second differential mixer.

12. The receiver of claim 9, wherein the second differential IF filter is external to the substrate.

13. The receiver of claim 9, further comprising a differential amplifier coupled between the first differential mixer and the first differential IF filter.

14. The receiver of claim 9, further comprising a differential amplifier coupled between the first differential IF filter and the second differential mixer.

15. The receiver of claim 9, wherein the first IF signal and the second IF signal are differential.

16. The receiver of claim 15, wherein the third IF signal is differential.

17. The receiver of claim 9, wherein the second differential mixer is an I/Q differential mixer that provides image rejection.

18. The receiver of claim 9, further comprising a means for adjusting a frequency of the first local oscillator so that a selected channel of the plurality of channels falls in a passband of the first differential IF filter.

19. The receiver of claim 18, wherein a frequency of the second local oscillator is determined so the selected channel falls in a passband of a second differential IF filter that is connected to an output of the second differential mixer.

20. The receiver of claim 9, wherein the plurality of channels include a plurality of television channels.

21. The receiver of claim 9, further comprising a low noise amplifier having a differential output coupled to an input of the first differential mixer.

22. The receiver of claim 12, fixer comprising a variable gain amplifier, disposed on the substrate and coupled to the output of the second differential IF filter.