Method and system for dynamic duration burn-in

• US 6,377,897 B1
• Filed: 08/31/2000
• Issued: 04/23/2002
• Est. Priority Date: 02/26/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rogers, Denzil, Boyington, Rick
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US09/652,621
• Time in Patent Office: 600 Days
• Field of Search: 702/118, 702/81, 702/87, 716/4, 324/527, 324/528, 324/760, 438/17, 438/18
• US Class Current: 702/81
• CPC Class Codes: G01R 31/287 Procedures; Software aspects

Abstract

A computer-implemented method and system for dynamic duration burn-in. A computer system is provided having a processing unit, input device and storage. The storage includes a performance database for tracking burn-in test results of a plurality of ICs. Test criteria is determined against which the burn-in test results will be compared. The plurality of ICs are stressed for a burn-in interval in a stress chamber and the plurality of ICs are tested to determine a failure rate from burn-in. The failure rate is compared to the test criteria and the steps of stressing, testing and comparing are repeated until the failure rate fulfills the test criteria.

Claims

1. A method for performing a burn-in test of integrated circuits, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for the integrated circuits approaches a random failure rate; and

terminating the burn-in test upon reaching the acceptable performance rate.

2. The method of claim 1, wherein the method further comprises determining a minimum time for stressing the integrated circuits based on historical data.

3. The method of claim 1, wherein collecting performance data comprises writing the performance data to a performance database.

4. The method of claim 1, further comprising calculating a failure rate for the integrated circuits from the performance data.

5. A method for performing a burn-in test of integrated circuits, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for failed integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the acceptable performance rate.

6. A method for performing a burn-in test of integrated circuits, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether a hazard rate for integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the random failure rate.

7. The method of claim 6, further comprising dynamically updating the performance database to improve accuracy in determining the random failure rate.

8. The method of claim 6, wherein the performance database includes information selected from the set consisting of:

delta and hazard values for a lot at each of the read points;

a delta and hazard pass/fail status;

a minimum burn-in time;

a burn-in interval between read points;

a passing read point;

an infant mortality failure read point;

a latent mortality failure read point; and

a predicted passing read point.

9. A method for performing a burn-in test of integrated circuits, comprising:

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.

10. The method of claim 9, wherein determining a minimum burn-in time comprises calculating a core time for stressing the integrated circuits from historical data.

11. The method of claim 9, wherein determining a failure rate comprises:

writing performance data obtained by testing the integrated circuits to a performance database; and

calculating a failure rate of the integrated circuits from the performance data.

12. The method of claim 9, wherein the random failure rate is determined by statistical analysis of past performance data extracted from a performance database.

13. A method for performing a burn-in test of integrated circuits, comprising:

determining a core time for stressing the integrated circuits from historical data;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points, including writing performance data to a performance database;

calculating a failure rate for integrated circuits as a function of the performance database;

determining whether a hazard rate for integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from the performance database;

dynamically updating the performance database to improve accuracy in determining the random failure rate; and

terminating the burn-in test upon reaching the random failure rate.

14. A method for manufacturing an integrated circuit, comprising:

fabricating a wafer;

segmenting the wafer into individual parts;

packaging the individual parts into integrated circuits; and

performing a burn-in process on the integrated circuits to detect infant mortalities, including;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for the integrated circuits approaches a random failure rate; and

terminating the burn-in test upon reaching the acceptable performance rate.

15. The method of claim 14, wherein the method further comprises determining a minimum time for stressing the integrated circuits based on historical data.

16. The method of claim 14, wherein collecting performance data comprises writing the performance data to a performance database.

17. The method of claim 14, further comprising calculating a failure rate for the integrated circuits from the performance data.

18. A method for manufacturing an integrated circuit, comprising:

fabricating a wafer;

segmenting the wafer into individual parts;

packaging the individual parts into integrated circuits; and

performing a burn-in process on the integrated circuits to detect infant mortalities, including;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for failed integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the acceptable performance rate.

19. A method for manufacturing an integrated circuit, comprising:

fabricating a wafer;

segmenting the wafer into individual parts;

packaging the individual parts into integrated circuits; and

performing a burn-in process on the integrated circuits to detect infant mortalities, including;

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.

20. A method for manufacturing an integrated circuit, comprising:

fabricating a wafer;

segmenting the wafer into individual parts;

packaging the individual parts into integrated circuits; and

performing a burn-in process on the integrated circuits to detect infant mortalities, including;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether a hazard rate for the integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the random failure rate.

21. The method of claim 20, further comprising dynamically updating the performance database to improve accuracy in determining the random failure rate.

22. The method of claim 20, wherein the performance database includes information selected from the set consisting of:

delta and hazard values for a lot at each of the read points;

a delta and hazard pass/fail status;

a minimum burn-in time;

a burn-in interval between read points;

a passing read point;

an infant mortality failure read point;

a latent mortality failure read point; and

a predicted passing read point.

23. A method for manufacturing an integrated circuit, comprising:

fabricating a wafer;

segmenting the wafer into individual parts;

packaging the individual parts into integrated circuits; and

performing a burn-in process on the integrated circuits to detect infant mortalities, including;

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.

24. A computer-implemented method for performing a burn-in test of integrated circuits, comprising:

providing a computer system including a processor, an input device and storage, wherein the storage includes an operating system, burn-in software, and a performance database;

providing a stress chamber;

providing burn-in test hardware interfaced with the computer system;

connecting the integrated circuits to the burn-in test hardware, and placing the combination in the stress chamber;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points, including writing the performance data to the performance database;

calculating a failure rate for the integrated circuits from the performance data;

determining whether the integrated circuits have reached an acceptable performance rate;

terminating the burn-in test upon reaching the acceptable performance rate, and

dynamically updating the performance database to improve accuracy in determining the random failure rate.

25. A computer-implemented method for performing a burn-in test of integrated circuits, comprising:

providing a computer system including a processor, an input device and storage, wherein the storage includes an operating system, burn-in software, and a performance database;

providing a stress chamber;

providing burn-in test hardware interfaced with the computer system;

connecting the integrated circuits to the burn-in test hardware, and placing the combination in the stress chamber;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points, including writing the performance data to the performance database;

calculating a failure rate for the integrated circuits from the performance data;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for failed integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from the performance database, and

terminating the burn-in test upon reaching the acceptable performance rate.

26. A computer-implemented method for performing a burn-in test of integrated circuits, comprising:

providing a computer system including a processor, an input device and storage, wherein the storage includes an operating system, burn-in software, and a performance database;

connecting the integrated circuits to burn-in test hardware within a stress chamber, wherein the burn-in test hardware is interfaced to the computer system;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points, including writing the performance data to the performance database;

calculating a failure rate for the integrated circuits from the performance data;

determining whether the integrated circuits have reached an acceptable performance rate;

dynamically updating the performance database to improve accuracy in determining the acceptable performance rate; and

terminating the burn-in test upon reaching the acceptable performance rate.

27. A computer-implemented method for performing a burn-in test of integrated circuits, comprising:

providing a computer system including a processor, an input device and storage, wherein the storage includes an operating system, burn-in software, and a performance database;

providing a stress chamber;

providing burn-in test hardware interfaced with the computer system;

connecting the integrated circuits to the burn-in test hardware, and placing the combination in the stress chamber;

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.

28. A computer readable medium encoded with a computer program, wherein the computer program executes a dynamic burn-in process, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

calculating a failure rate for the integrated circuits from the performance data;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for integrated circuits approaches a random failure rate; and

terminating the burn-in test upon reaching the acceptable performance rate.

29. The computer readable medium of claim 28, wherein the process further comprises determining a minimum time for stressing the integrated circuits based on historical data.

30. The computer readable medium of claim 28, wherein collecting performance data comprises writing performance data to a performance database.

31. A computer readable medium encoded with a computer program, wherein the computer program executes a dynamic burn-in process, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

calculating a failure rate for the integrated circuits from the performance data;

determining whether the integrated circuits have reached an acceptable performance rate, including determining whether a hazard rate for failed integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the acceptable performance rate.

32. A computer readable medium encoded with a computer program, wherein the computer program executes a dynamic burn-in process, comprising:

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

generating a curve of failed integrated circuits from the performance data;

determining whether a hazard rate for integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from a performance database; and

terminating the burn-in test upon reaching the random failure rate.

33. The computer readable medium of claim 32, wherein the process further comprises dynamically updating the performance database to improve accuracy in determining the random failure rate.

34. The computer readable medium of claim 32, wherein the performance database includes information selected from the set consisting of:

delta and hazard values for a lot at each of the read points;

a delta and hazard pass/fail status;

a minimum burn-in time;

a burn-in interval between read points;

a passing read point;

an infant mortality failure read point;

a latent mortality failure read point; and

a predicted passing read point.

35. A computer readable medium encoded with a computer program, wherein the computer program executes a dynamic burn-in process, comprising:

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.

36. A device, comprising:

a stress chamber;

burn-in test hardware adapted for receiving integrated circuits and for being positioned in the stress chamber; and

a computer system interfaced with the burn-in test hardware, the computer system including a processor and a computer readable medium encoded with a burn-in software program and a performance database, wherein the computer system controls a dynamic burn-in process, comprising;

stressing the integrated circuits;

collecting performance data regarding the integrated circuits at intermittent read points;

determining whether a hazard rate for the integrated circuits approaches a random failure rate as determined by statistical analysis of past performance data extracted from the performance database; and

terminating the burn-in test upon reaching the random failure rate.

37. The device of claim 36, wherein the process further comprises dynamically updating the performance database to improve accuracy in determining the random failure rate.

38. The device of claim 36, wherein the performance database includes information selected from the set consisting of:

delta and hazard values for a lot at each of the read points;

a delta and hazard pass/fail status;

a minimum burn-in time;

a burn-in interval between read points;

a passing read point;

an infant mortality failure read point;

a latent mortality failure read point; and

a predicted passing read point.

39. A device, comprising:

a stress chamber;

burn-in test hardware adapted for receiving integrated circuits and for being positioned in the stress chamber; and

a computer system interfaced with the burn-in test hardware, the computer system including a processor and a computer readable medium encoded with a burn-in software program and a performance database, wherein the computer system controls a dynamic burn-in process, comprising;

determining a minimum burn-in time;

stressing the integrated circuits during the burn-in time;

testing the integrated circuits intermittently at read points during the burn-in time;

determining a failure rate for the integrated circuits at each of the read points; and

upon completing the minimum time, stopping the stressing and testing when the failure rate approaches a random failure rate.