Emulation system with time-multiplexed interconnect
First Claim
1. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:
- a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having logic elements capable of implementing combinatorial logic elements and sequential logic elements, said reprogrammable logic devices also comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection, said reprogrammable logic devices further comprising a first clock divider, said clock divider receiving a multiplexing clock signal;
a plurality of reprogrammable interconnect devices disposed on said printed circuit board, said plurality of reprogrammable interconnect devices comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal of said plurality of reprogrammable interconnect devices, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection, each of said plurality of reprogrammable interconnect devices comprising configurable interconnect circuitry which places said input demultiplexers in electrical communication with said output multiplexers, said reprogrammable interconnect devices further comprising a second clock divider, said clock divider receiving said multiplexing clock signal; and
a set of fixed electrical conductors of said printed circuit board connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices.
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Accused Products
Abstract
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
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Citations
45 Claims
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1. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable logic assembly comprising:
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a plurality of reprogrammable logic devices disposed on a printed circuit board, each of said reprogrammable logic devices having logic elements capable of implementing combinatorial logic elements and sequential logic elements, said reprogrammable logic devices also comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection, said reprogrammable logic devices further comprising a first clock divider, said clock divider receiving a multiplexing clock signal;
a plurality of reprogrammable interconnect devices disposed on said printed circuit board, said plurality of reprogrammable interconnect devices comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal of said plurality of reprogrammable interconnect devices, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection, each of said plurality of reprogrammable interconnect devices comprising configurable interconnect circuitry which places said input demultiplexers in electrical communication with said output multiplexers, said reprogrammable interconnect devices further comprising a second clock divider, said clock divider receiving said multiplexing clock signal; and
a set of fixed electrical conductors of said printed circuit board connecting said programmable input/output terminals on said reprogrammable logic devices to said input/output terminals on said reprogrammable interconnect devices such that each of said reprogrammable interconnect devices is connected to at least one but not all of said programmable input/output terminals on each of said reprogrammable logic devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system having a user'"'"'s circuit design implemented therein, said electrically reconfigurable logic assembly comprising:
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a plurality of reprogrammable logic devices installed on a printed circuit board, each of said reprogrammable logic devices having internal circuitry which can be reprogrammably configured to provide at least combinatorial logic elements and sequential logic elements, said reprogrammable logic devices also comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal, said input demultiplexer receiving a time-multiplexed signal and dividing said time-multiplexed signal into one or more internal signals, said output multiplexer combining one or more internal signals onto a first single physical interconnection, said reprogrammable logic devices further comprising a first clock divider, said clock divider receiving a multiplexing clock signal;
a plurality of reprogrammable interconnect devices disposed on said printed circuit board, said plurality of reprogrammable interconnect devices comprising an input demultiplexer and an output multiplexer implemented at at least one input/output terminal of said plurality of reprogrammable interconnect devices, said input demultiplexer receiving a time-multiplexed input signal and dividing it into one or more component signals, said output multiplexer combining said one or more component signals or other component signals onto a second single physical interconnection, each of said plurality of reprogrammable interconnect devices comprising configurable interconnect circuitry which places said input demultiplexers in electrical communication with said output multiplexers, said reprogrammable interconnect devices further comprising a second clock divider;
said clock divider receiving said multiplexing clock signal; and
a set of fixed electrical conductors of said printed circuit board, said set of fixed electrical conductors interconnecting said reprogrammable logic devices to said reprogrammable interconnect devices with a partial crossbar architecture. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification