System having double data transfer rate and intergrated circuit therefor

• US 6,378,020 B2
• Filed: 04/10/2000
• Issued: 04/23/2002
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/545,648
• Publication Number:
  US 20020016876A1
• Time in Patent Office: 743 Days
• Field of Search: 710/100, 710/126, 710/128, 710/129, 710/35, 365/233, 365/235, 365/238.05
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal. The output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal. The integrated circuit device may further include input receiver circuitry to sample data from a second external signal line. The input receiver circuitry samples a first portion of data in response to a rising edge transition of a second external clock signal. The input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

Claims

1. A system comprising:

a first integrated circuit device coupled to an external signal line, the first integrated circuit device including;

output driver circuitry to output data onto the external signal line wherein;

the output driver circuitry outputs a first portion of data in response to a rising edge transition of an external clock signal; and

the output driver circuitry outputs a second portion of data in response to a falling edge transition of the external clock signal; and

a second integrated circuit device coupled to the external signal line, the second integrated circuit device including;

output driver circuitry to output data onto the external signal line wherein;

the output driver circuitry outputs a first portion of data in response to a rising edge transition of the external clock signal; and

the output driver circuitry outputs a second portion of data in response to a falling edge transition of the external clock signal.

2. The system of claim 1 further including a clock generator coupled to a second external signal line to generate the external clock signal, wherein the first and second integrated circuit devices are each coupled to the second external signal line.

3. The system of claim 1 wherein the first and second integrated circuit devices each include a clock alignment circuit coupled to the output driver circuitry.

4. The system of claim 3 wherein each clock alignment circuit is a delay lock loop circuit to generate an internal clock signal, and wherein the output driver circuitry outputs data in response to the internal clock signal.

5. The system of claim 1 wherein the first and second integrated circuit devices each further include:

multiplexer circuitry coupled to the output driver circuitry, wherein;

in response to a first transition of the external clock signal, the multiplexer circuitry couples the first portion of data to an input of the output driver circuitry; and

in response to a second transition of the external clock signal, the multiplexer circuitry couples the second portion of data to the input of the output driver circuitry.

6. The system of claim 5 wherein the first and second integrated circuit devices each further include a clock alignment circuit to generate a first internal clock signal, and wherein the multiplexer circuitry couples the first portion of data to the input of the output driver circuitry in response to the first internal clock signal.

7. The system of claim 6 wherein the clock alignment circuit generates a second internal clock signal, and wherein the multiplexer circuitry couples the second portion of data to the input of the output driver circuitry in response to the second internal clock signal.

8. The system of claim 1 wherein both the rising edge transition of the external clock signal and the falling edge transition of the external clock signal transpire during a first clock cycle of the external clock signal.

9. The system of claim 1 wherein both the rising and falling edge transitions of the external clock signal each include a voltage swing of less than one volt.

10. The system of claim 1 wherein the first and second integrated circuit devices each further include:

input receiver circuitry to sample data from the external signal line wherein;

the input receiver circuitry samples a first portion of data in response to a rising edge transition of the external clock signal; and

the input receiver circuitry samples a second portion of data in response to a falling edge transition of the external clock signal.

11. A system comprising:

a first integrated circuit device coupled to an external signal line, the first integrated circuit device including;

output driver circuitry to output data onto the external signal line wherein;

the output driver circuitry outputs a first portion of data synchronously with respect to a rising edge transition of an external clock signal; and

the output driver circuitry outputs a second portion of data synchronously with respect to a falling edge transition of the external clock signal; and

a second integrated circuit device coupled to the external signal line, the second integrated circuit device including;

input driver circuitry to sample data from the external signal line wherein;

the input receiver circuitry samples the first portion of data synchronously with respect to the rising edge transition of the external clock signal; and

the input receiver circuitry samples the second portion of data synchronously with respect to the falling edge transition of the external clock signal.

12. The system of claim 11 further including a clock generator coupled to a second external signal line to generate the external clock signal, wherein the first and second integrated circuit devices receive the external clock signal.

13. The system of claim 11 wherein the first integrated circuit device further includes a clock alignment circuit to receive the external clock signal and to generate an internal clock signal, wherein the output driver circuitry outputs data in response to the internal clock signal.

14. The system of claim 11 wherein the first integrated circuit device further includes:

multiplexer circuitry coupled to the output driver circuitry, wherein;

in response to a first transition of the external clock signal, the multiplexer circuitry couples the first portion of data to an input of the output driver circuitry; and

in response to a second transition of the external clock signal, the multiplexer circuitry couples the second portion of data to the input of the output driver circuitry.

15. The system of claim 11 wherein both the rising edge transition of the external clock signal and the falling edge transition of the external clock signal transpire during a first clock cycle of the external clock signal.

16. The system of claim 11 wherein both the rising and falling edge transitions of the external clock signal include voltage swings of less than one volt.

17. The system of claim 11 wherein the second integrated circuit further includes a clock alignment circuit to receive the external clock signal and to generate an internal clock signal, wherein the input receiver circuitry on the second integrated circuit device samples data in response to the internal clock signal.

18. An integrated circuit device comprising:

first output driver circuitry to output data onto a first external signal line wherein;

the first output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal and the first output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal; and

second output driver circuitry to output data onto a first external signal line wherein;

the second output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal and the second output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal.

19. The integrated circuit device of claim 18 further including input receiver circuitry to sample data from a second external signal line wherein:

the input receiver circuitry samples a first portion of data in response to a rising edge transition of the second external clock signal; and

the input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

20. The integrated circuit device of claim 19 further including a clock alignment circuit to generate a first internal clock signal, and wherein the input receiver circuitry samples the first portion of data in response to the first internal clock signal.

21. The integrated circuit device of claim 20 wherein the clock alignment circuit generates a second internal clock signal, and the input receiver samples the second portion of data in response to the second internal clock signal.

22. The integrated circuit device of claim 18 wherein a clock alignment circuit generates an internal clock signal, and the first output driver circuitry and the second output driver circuitry output data in response to the internal clock signal.

23. The integrated circuit device of claim 18 further including input receiver circuitry to sample data from the first external signal line wherein:

the input receiver circuitry samples a first portion of data in response to a rising edge transition of the first external clock signal; and

the input receiver circuitry samples a second portion of data in response to a falling edge transition of the first external clock signal.

24. The integrated circuit device of claim 18 further including:

multiplexer circuitry coupled to the first output driver circuitry, wherein;

in response to a first transition of the first external clock signal, the multiplexer circuitry couples the first portion of data to an input of the first output driver circuitry; and

in response to a second transition of the first external clock signal, the multiplexer circuitry couples the second portion of data to the input of the first output driver circuitry.

25. The integrated circuit device of claim 24 further including a clock alignment circuit to generate a first internal clock signal using the first external clock signal, wherein the multiplexer circuitry couples the first portion of data to the input of the first output driver circuitry in response to the first internal clock signal.

26. The integrated circuit device of claim 25 wherein the clock alignment circuit generates a second internal clock signal, and wherein the multiplexer circuitry couples the second portion of data to the input of the first output driver circuitry in response to the second internal clock signal.

27. The integrated circuit device of claim 24 further including a clock alignment circuit to generate a first internal clock signal using the first external clock signal, wherein the multiplexer circuitry couples the first portion of data to the input of the first output driver circuitry in response to the first internal clock signal.

28. The integrated circuit device of claim 18 wherein both the rising edge transition of the first external clock signal and the falling edge transition of the first external clock signal transpire during a first clock cycle of the first external clock signal.

29. The integrated circuit device of claim 18 wherein both the rising and falling edge transitions of the first external clock signal include voltage swings of less than one volt.

30. An integrated circuit device comprising:

input receiver circuitry to sample an operation code synchronously with respect to a first transition of an external clock signal, the operation code specifying a read operation; and

output driver circuitry to output data in response to the operation code, wherein;

the output driver circuitry outputs a first portion of data in response to a rising edge transition of the external clock signal; and

the output driver circuitry outputs a second portion of data in response to a falling edge transition of the external clock signal.

31. The integrated circuit device of claim 30 further including a memory array having a plurality of memory cells.

32. The integrated circuit device of claim 31 wherein the input receiver circuitry receives address information synchronously with respect to the external clock signal.

33. The integrated circuit device of claim 32 wherein the input receiver circuitry samples the address information synchronously with respect to a second transition of the external clock signal.

34. The integrated circuit device of claim 32 wherein the operation code and the address information are included in a packet.

35. The integrated circuit device of claim 30 further including a clock alignment circuit to receive the external clock signal.

36. The integrated circuit device of claim 35 wherein the clock alignment circuit generates an internal clock signal, and the output driver circuitry outputs data in response to the internal clock signal.

37. The integrated circuit device of claim 30 wherein both the rising and falling edge transitions of the external clock signal include voltage swings of less than one volt.

38. The integrated circuit device of claim 30 wherein the rising edge transition of the external clock signal and the falling edge transition of the external clock signal transpire in one clock cycle of the external clock signal.

39. The integrated circuit device of claim 30 wherein the input receiver circuitry receives block size information synchronously with respect to the external clock signal, wherein the block size information indicates an amount of data to be output by the output driver circuitry.

40. The integrate circuit device of claim 30 wherein the input receiver circuitry receives a value which is representative of a number of clock cycles of the external clock signal to transpire before the output driver circuitry outputs data.

41. The integrated circuit device of claim 40 further including a programmable register to store the value which is representative of a number of clock cycles of the external clock signal to transpire before the output driver circuitry outputs data.