Power bus and method for generating power slits therein

• US 6,378,120 B2
• Filed: 01/12/2001
• Issued: 04/23/2002
• Est. Priority Date: 02/10/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hoang, Hy, Chuang, Tatao, Long, Tran, Lin, Chong Ming
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/758,367
• Publication Number:
  US 20010002318A1
• Time in Patent Office: 466 Days
• Field of Search: 716/8, 716/9, 716/10
• US Class Current: 716/54
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Claims

1. A method for generating power slits in a power bus located on a chip, comprising the steps of:

(a) locating the data set representing the power bus in a mask layout database;

(b) determining a width for the power bus;

(c) determining a length for the power bus;

(d) dividing said width of the power bus by a first width of the power slits plus a first spacing distance between a first number of power slits to be generated in a first direction of the power bus;

(e) dividing said length of the power bus by a first length of the power slits plus a second spacing distance between the power slits to determine a second number of power slits to be generated in a second direction of the power bus; and

(f) automatically adding a location of the power slits determined in said steps (d) and (e) to said data set representing the power bus on the mask layout database.

2. A method according to claim 1, wherein said steps (b) and (c) further comprise the steps of:

(i) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in said first direction;

(ii) subtracting said starting-point from said endpoint resulting in a first absolute value;

(iii) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in said second direction;

(iv) subtracting said starting-point and said endpoint resulting in a second absolute value;

(v) comparing said first value with said second value to determine which is greater;

(vi) assigning said greater value as said length of the power bus; and

(vii) assigning which ever value is smaller according to step (v) as said width of the power bus.

3. A method according to claim 2, wherein said starting-points and said endpoints are coordinate locations obtained from the data set representing the power bus on the mask layout database.

4. A method according to claim 1, wherein said step (b) further comprises the steps of comparing said width to a minimum standard value and returning to step (a) if said minimum standard value is greater than said width for the power bus.

5. A method according to claim 1, wherein said steps (a)-(f) are repeated until all power buses in a defined region of the mask layout database have power slits.

6. A power bus, comprising:

a first axis and a second axis, wherein power flows in the direction of said first axis; and

a plurality of power slits located along said first axis and said second axis of the power bus, wherein said power slits are formed by the steps of;

(a) determining a width for the power bus;

(b) determining a length for the power bus;

(c) dividing said width of the power bus by a first width of said power slits plus a first spacing distance between said power slits to determine a first number of power slits to be generated in a first direction of the power bus;

(d) dividing said length of the power bus by a first length of said power slits plus a second spacing distance between said power slits to determine a second number of power slits to be generated in a second direction of the power bus; and

(e) automatically adding a location of the power slits determined in said steps (c) and (d) to a data set representing the power bus in a mask layout database.

7. A power bus according to claim 6, wherein said steps (c) and (d) further comprise the steps of:

(i) assigning a starting-point and an endpoint corresponding to boundaries of the data set representing the power bus in said first direction;

(ii) subtracting said starting-point from said endpoint resulting in a first absolute value;

(iii) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in said direction;

(iv) subtracting said starting-point and said endpoint resulting in a second absolute value;

(v) comparing said first value with said second value to determine which is greater;

(vi) assigning said greater value as said length of the power bus; and

(vii) assigning which ever value is smaller according to step (v) as said width of the power bus.

8. A power bus according to claim 7, wherein said starting-point and said endpoints are coordinate values obtained from the mask layout data base.