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Power bus and method for generating power slits therein

  • US 6,378,120 B2
  • Filed: 01/12/2001
  • Issued: 04/23/2002
  • Est. Priority Date: 02/10/1992
  • Status: Expired due to Fees
First Claim
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1. A method for generating power slits in a power bus located on a chip, comprising the steps of:

  • (a) locating the data set representing the power bus in a mask layout database;

    (b) determining a width for the power bus;

    (c) determining a length for the power bus;

    (d) dividing said width of the power bus by a first width of the power slits plus a first spacing distance between a first number of power slits to be generated in a first direction of the power bus;

    (e) dividing said length of the power bus by a first length of the power slits plus a second spacing distance between the power slits to determine a second number of power slits to be generated in a second direction of the power bus; and

    (f) automatically adding a location of the power slits determined in said steps (d) and (e) to said data set representing the power bus on the mask layout database.

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