Method of handling macro components in circuit design synthesis

• US 6,378,123 B1
• Filed: 02/20/1998
• Issued: 04/23/2002
• Est. Priority Date: 02/20/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dupenloup, Guy
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US09/027,429
• Time in Patent Office: 1,523 Days
• Field of Search: 395/500.19, 395/500.03, 395/500.04, 395/500.08, 395/500.09, 395/500.11, 395/500.12, 716/2, 716/3, 716/7, 716/8, 716/10, 716/11, 716/18
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method of synthesizing integrated circuit (IC) design having DesignWare components comprising the steps of initially mapping DesignWare components, revising DesignWare component structure, ungrouping DesignWare components, and re-synthesizing DesignWare components. The step of initially mapping is performed using elaborate command and compile command of a logic synthesis tool. The step of ungrouping DesignWare components involves dissolving DesignWare modules to be merged with surrounding logic.

Claims

1. A method of synthesizing an integrated circuit (IC) design, said method comprising the steps of:

a. initially mapping said IC design into components in a target technology, said step a including selection of a structured logic module from a technology library to be included among said components, wherein said structured logic module has a structure that has been predefined;

b. after step a, revising the structure of the structured logic module;

c. after determining that there is no further need to revise the structure of the structured logic module, ungrouping the structured logic module; and

d. after step c, re-synthesizing said components.

2. A method according to claim 1 wherein said step a is performed using an elaborate command and a compile command of a logic synthesis tool.

3. A method according to claim 1 wherein said step d includes removing unused input/output ports of the logic components.

4. A method according to claim 1, further comprising a step of identifying the structured logic module based on a naming convention prior to said step c.

5. A method according to claim 1 wherein said step b is performed during a re-synthesis operation prior to said step d.

6. A method of generating synthesis scripts for synthesizing an integrated circuit (IC) design, said method comprising the step of generating a synthesis script to cause a synthesis tool to:

a. initially map said IC design into components in a target technology, said step a including selection of a structured logic module from a technology library to be included among said components, wherein said structured logic module has a structure that has been predefined;

b. after step a, revise the structure of the structured logic module;

c. after determining that there is no further need to revise the structure of the structured logic module, ungroup the structured logic module; and

d. after step c, re-synthesize said components.

7. A method according to claim 6 wherein said synthesis script is for a dc shell environment.

8. A method of synthesizing an integrated circuit (IC) design, said method comprising the steps of:

a. initially mapping said IC design into components in a target technology, said step a including selection of a structured logic module from a technology library to be included among said components, wherein said structured logic module has a structure that has been predefined;

b. after step a, characterizing the components so as to obtain new constraints; and

c. after step b, re-synthesizing said components, said step c including revising the structure of the structured logic module based on the new constraints;

d. after determining that there is no further need to revise the structure of the structured logic module, ungrouping the structured logic module;

e. after step d, re-synthesizing said components.

9. A method according to claim 8, further comprising a step of repeating steps b and c.

10. A method according to claim 8 wherein said step e includes removing unused input/output ports of the logic components.

11. A method according to claim 8, further comprising a step of identifying the structured logic module based on a naming convention prior to said step d.