Process for forming electrodes

• US 6,379,509 B2
• Filed: 01/20/1998
• Issued: 04/30/2002
• Est. Priority Date: 01/20/1998
• Status: Expired due to Term

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Chu, Yi Zhu, Choi, Hyung-Chul, Smyth, William K., Heath, Linda S.
• Primary Examiner(s): Nguyen, Nam
• Assistant Examiner(s): Cantelmo, Gregg
• Application Number:
  US09/009,391
• Publication Number:
  US 20010050222A1
• Time in Patent Office: 1,561 Days
• Field of Search: 204/192.29, 204/192.12, 204/192.15, 204/192.3, 427/126.1, 427/126.3, 427/162, 427/164, 427/166, 357/30
• US Class Current: 204/192.29
• CPC Class Codes: C09K 2323/00 Functional layers of liquid crystal optical display excluding electroactive liquid crystal layer characterised by chemical composition
• CPC Class Codes: C09K 2323/051 Inorganic, e.g. glass or silicon oxide
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: Y10T 428/24942 including components having same physical characteristic in differing degree
• CPC Class Codes: Y10T 428/261 In terms of molecular thickness or light wave length

Abstract

Substantially transparent electrodes are formed upon a substrate by forming on the substrate, in order, a high index layer, a metallic conductive layer, and a conductive or semi-conductive top layer; and patterning the top layer and the conductive layer, preferably by laser ablation, to form a plurality of discrete electrodes from the metallic conductive layer. Conductors can be attached directly to the top layer, without requiring removal of this layer to expose the metallic conductive layer. The high index layer, conductive layer and top layer can all be formed by sputtering or similar processes which do not require high temperatures, so that plastic substrates can be used. The electrodes can be used, for example, in flat panel displays and in touch screen displays.

Claims

1. A process for forming a plurality of substantially transparent electrodes upon a substrate, the process comprising:

forming on the substrate, in order, a bottom high index layer, a metallic conductive layer comprising a layer of silver coated with a layer of gold that is thinner than the layer of silver, and a top high index layer, said top high index layer having a conductivity of at least about 400 ohms/square and

patterning the top high index layer and the conductive layer to form a plurality of discrete electrodes from the metallic conductive layer.

2. A process according to claim 1 further comprising connecting a plurality of conductors to portions of the top high index layer overlying the discrete electrodes.

3. A process according to claim 1 wherein the substrate comprises a synthetic resin.

4. A process according to claim 1 wherein the bottom high index layer is an electrically insulating layer.

5. A process according to claim 1 wherein the bottom high index layer comprises at least one of indium oxide, titanium dioxide, cadmium oxide, gallium indium oxide, niobium pentoxide, indium tin oxide and tin dioxide.

6. A process according to claim 1 wherein the bottom high index layer is formed by sputtering.

7. A process according to claim 3 wherein the bottom high index layer is formed at a temperature not greater than about 170°

C.

8. A process according to claim 1 wherein the conductive layer is formed by sputtering.

9. A process according to claim 3 wherein the conductive layer is formed at a temperature not greater than about 170°

C.

10. A process according to claim 1 wherein the top high index layer comprises at least one of indium oxide, titanium dioxide, cadmium oxide, gallium indium oxide, niobium pentoxide, indium tin oxide and tin dioxide.

11. A process according to claim 1 wherein the top high index layer is formed by sputtering.

12. A process according to claim 3 wherein the top high index layer is formed at a temperature not greater than about 170°

C.

13. A process according to claim 1 wherein the thickness of the layer of gold is from about 1 nm to about 1.5 nm.