Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing

• US 6,379,982 B1
• Filed: 08/17/2000
• Issued: 04/30/2002
• Est. Priority Date: 08/17/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LUK, OLIVIA T
• Application Number:
  US09/640,739
• Time in Patent Office: 621 Days
• Field of Search: 438/106, 438/459, 438/14, 438/15, 438/16, 324/158, 324/754, 324/755, 324/765, 324/760
• US Class Current: 438/14
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same. The wafer-on-wafer package can be burned-in and tested at the wafer level prior to segmenting, or singulating, the wafer-on-wafer package into a plurality of individual chip-scale packages. The device wafer includes a plurality of unsingulated semiconductor dies having a plurality of die bond pads being respectively bonded to a plurality of electrically conductive die bond pad connect elements provided on a first surface of the support wafer. The die bond pad connect elements are in electrical communication with a plurality of respectively associated test connection/mounting elements positioned in a prearranged pattern on the opposite surface of the support wafer. Preferably the die bond pad connect elements and the test connection/mounting elements are placed in electrical communication by way of electrical paths extending through vias, or feed-throughs, provided in the support wafer. Upon burning-in and testing the wafer-on-wafer package, chip-scale packages are singulated from the wafer-on-wafer package and the test connection/mounting elements of the chip-scale package are bonded to respective, corresponding mounting pads, or other suitable surfaces located on circuit boards, memory modules, or other substrates. The wafer-on-wafer package and chip-scale packages of the present invention are particularly well-suited for use in the production of semiconductor chips and packages incorporating ultra large-scale integration (ULSI) technology as well as bonding techniques such as controlled collapse chip connection (C4) techniques.

Claims

1. A method of constructing a wafer-on-wafer semiconductor package comprising:

providing a semiconductor device wafer having at least one active surface and an opposite surface, the semiconductor device wafer comprising a plurality of unsingulated semiconductor dies having die bond pads exposed on the at least one active surface of the semiconductor device wafer;

providing a support wafer having a die connect surface and a testing/mounting surface of the support wafer;

forming a plurality of vias arranged in a preselected pattern, the plurality of vias extending from the die connect surface of the support wafer to the testing/mounting surface of the support wafer;

disposing a plurality of electrically conductive traces on the die connect surface of the support wafer, the plurality of electrically conductive traces each having a prepositioned die bond pad connect element end and a via end terminating at one of the plurality of vias;

locating and forming a plurality of electrically conductive die bond pad connect elements on the die connect surface of the support wafer, the plurality of electrically conductive die bond pad connect elements each being in electrical communication with selected said die bond pad connect element ends of the electrically conductive traces;

introducing a volume of an electrically conductive material within at least some of the plurality of vias, the volume of the electrically conductive material completing an electrical path between selected said plurality of electrically conductive die bond pad connect elements respectively associated with the at least some of the plurality of vias and terminating in a first meniscus proximate the testing/mounting surface of the support wafer to provide a plurality of test connection/mounting elements; and

attaching the plurality of electrically conductive die bond pad connect elements to the die bond pads to mechanically and electrically connect the semiconductor device wafer to the support wafer to create the wafer-on-wafer semiconductor package.

2. The method of claim 1, wherein the forming the plurality of electrically conductive die bond pad connect elements comprises forming a plurality of electrically conductive globules of a preselected material.

3. The method of claim 1, wherein disposing the plurality of electrically conductive traces comprises disposing electrically conductive traces comprising copper.

4. The method of claim 3, wherein disposing the plurality of electrically conductive traces comprises disposing electrically conductive traces having a thickness not exceeding approximately 10 μ

m.

5. The method of claim 2, wherein forming the plurality of electrically conductive die bond pad connect elements comprises forming the plurality of electrically conductive globules from a preselected reflowable solder material.

6. The method of claim 2, wherein forming the plurality of electrically conductive globules comprises forming the plurality of electrically conductive globules of a material comprising at least one metal.

7. The method of claim 6, wherein attaching the plurality of electrically conductive die bond pad connect elements to the die bond pads comprises using controlled collapsed chip connection bonding techniques.

8. The method of claim 1, wherein forming the plurality of vias comprises forming the plurality of vias by at least one of the processes of the group consisting of etching, laser drilling, and electrochemical anodization.

9. The method of claim 1, wherein introducing the volume of the electrically conductive material within the at least some of the plurality of vias comprises placing the support wafer in a bath of the electrically conductive material which has been heated to an elevated temperature.

10. The method of claim 9, wherein the placing the support wafer in the bath of the electrically conductive material comprises floating the support wafer in the bath of the electrically conductive material and wherein the bath of the electrically conductive material comprises lead and tin.

11. The method of claim 1, wherein introducing the volume of the electrically conductive material within the at least some of the plurality of vias results in forming a second meniscus on the die connect surface of the support wafer in electrical communication with one of the plurality of electrically conductive traces respectively associated with the at least some of the plurality of vias.

12. The method of claim 1, farther comprising disposing a thin film of metallic material comprising copper within the at least some of the plurality of vias.

13. The method of claim 12, wherein disposing the thin film of metallic material comprises disposing the thin film of metallic material by chemical vapor deposition.

14. The method of claim 1, further comprising providing a diffusion barrier within the at least some of the plurality of vias.

15. The method of claim 14, wherein providing the diffusion barrier comprises disposing the diffusion barrier within the at least some of the plurality of vias by chemical vapor deposition.

16. The method of claim 14, wherein providing the diffusion barrier within the at least some of the plurality of vias comprises forming a first layer of titanium oxide chemical vapor deposition followed by forming a second layer over the first layer by chemical vapor deposition, the second layer comprising a thin film of copper.

17. The method of claim 14, wherein providing the diffusion barrier within the at least some of the plurality of vias comprises providing an oxide layer formed at a temperature exceeding approximately 1000°

C.

18. The method of claim 14, wherein providing the diffusion barrier within the at least some of the plurality of vias comprises providing an oxide layer formed at a temperature not exceeding approximately 600°

C.

19. The method of claim 1, wherein providing the support wafer comprises obtaining a defective semiconductor device wafer having at least one defect rendering it nonsuitable for use as the semiconductor device wafer and using the defective semiconductor device wafer as the support wafer.

20. The method of claim 19, wherein obtaining the defective semiconductor device wafer comprises obtaining the defective semiconductor device wafer from the same production line which produced the semconductor device wafer.

21. The method of claim 1, wherein providing the support wafer and the providing the semiconductor device wafer comprises providing a semiconductor device wafer and providing a support wafer in which both wafers are of essentially identical material and are of essentially the same size and configuration.

22. The method of claim 21, wherein providing the support wafer and the providing the semiconductor device wafer comprises providing a semiconductor device wafer and providing a support wafer in which both wafers comprise at least one of the group consisting of silicon, geranium, silicon geranium, silicon carbide, gallium arsenide, selenium, and tellurium.

23. The method of claim 1, wherein providing the semiconductor device wafer comprises providing a semiconductor device wafer in which at least some of the plurality of unsingulated semiconductor dies each comprise ultra large-scale integration of active devices.

24. The method of claim 23, wherein providing the semiconductor device wafer comprises providing a semiconductor device wafer in which the at least some of the plurality of unsingulated semiconductor dies each comprise a quantity of active devices which exceeds approximately 100 million.

25. The method of claim 1, further comprising contacting at least some of the plurality of the test connection/mounting elements of the wafer-on-wafer semiconductor package with correspondingly positioned test probes.

26. The method of claim 25, farther comprising electrically exercising and testing the plurality of unsingulated semiconductor dies of the wafer-on-wafer semiconductor package at an elevated temperature.

27. The method of claim 26, further comprising actively removing heat from the opposite surface of the semiconductor device wafer when exercising the plurality of unsingulated semiconductor dies of the wafer-on-wafer semiconductor package.

28. The method of claim 26, further comprising identifying unsingulated semiconductor dies of the wafer-on-wafer package which are not successfully exercised and tested.