Semiconductor device and method of manufacturing the same

• US 6,379,999 B1
• Filed: 03/15/2000
• Issued: 04/30/2002
• Est. Priority Date: 09/10/1999
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Tanabe, Shinji
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Luu, Chuong A
• Application Number:
  US09/525,517
• Time in Patent Office: 776 Days
• Field of Search: 438/113, 438/114, 438/458, 438/106, 438/199, 438/202, 438/234, 438/460, 438/462, 438/110, 438/465, 438/617, 438/112, 438/124, 438/127, 438/122, 438/459, 438/455, 438/424, 257/684, 257/118, 257/513, 216/17, 216/52, 216/65-67
• US Class Current: 438/113
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method of manufacturing a semiconductor device in which potential can be applied well to a substrate without the semiconductor device being made less compact. A wafer 11A includes a semiconductor layer 13, a surface oxide film 14 and electrode pads 16 for the substrate. The semiconductor layer 13 is formed on the wafer 11A via an insulating layer 12, and a plurality of same semiconductor circuits are formed collectively at the semiconductor layer 13. The surface oxide film 14 covers the semiconductor layer 13. The electrode pads 16 for the substrate are formed on the surface oxide film 14 in correspondence with the semiconductor circuits. Cut grooves 18 for separating the wafer 11A into chips 10 of the semiconductor circuits are formed in the wafer 11A from the surface oxide film 14 to the substrate. Before the wafer 11A is separated into the chips 10, a conductive layer 17 is formed. The conductive layer 17 is formed from a substrate region 11 of cut groove surfaces 18a and 18b, via the cut groove surfaces 18a and 18b, and reaches the electrode pads 16.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming cut grooves in a wafer which becomes a substrate, the wafer including a semiconductor layer which is disposed on the wafer via an insulating layer and at which a plurality of same semiconductor circuits are formed collectively, a surface oxide film which covers the semiconductor layer, and electrode pads for electrical contact with the substrate, the electrode pads being formed on the surface oxide film in correspondence with the respective semiconductor circuits, the cut grooves being formed in the wafer from the surface oxide film to the substrate, for separating the wafer into chips of the respective semiconductor circuits; and

before separating the wafer into the chips, forming a conductive layer on groove surfaces of the cut grooves, the conductive layer extending from a substrate region via the groove surfaces of the cut grooves to the electrode pads.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the cut grooves are grid lines disposed in a lattice configuration.

3. A method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed by heating after a paste-like conductive material which hardens by heating is applied to predetermined places including the groove surfaces of the cut grooves.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the wafer is formed from silicon oxide and, together with the insulating layer and the semiconductor layer, forms an SOI structure.