Method to form an embedded flash memory circuit with reduced process steps

• US 6,380,031 B1
• Filed: 08/10/2000
• Issued: 04/30/2002
• Est. Priority Date: 09/08/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Xia, Jie, Zheng, Sandra, Mehrad, Freidoon, Tsung, Lancy
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/637,090
• Time in Patent Office: 628 Days
• Field of Search: 438/257, 438/258, 438/316, 438/266, 438/286, 438/201, 438/211, 438/317, 438/318, 438/319, 438/320, 438/321, 438/322
• US Class Current: 438/257
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).

Claims

1. A method of fabricating an embedded FLASH integrated circuit comprising:

forming a first photoresist film over a semiconductor substrate;

patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; and

partially etching said first region of said polycrystalline silicon film.

2. The method of claim 1 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.

3. The method of claim 1 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl₂/CF₄/HeO₂ plasma etch process.

4. The method of claim 1 further comprising the steps of:

removing said first photoresist film;

forming and patterning a second photoresist film; and

etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.

5. A method of fabricating an embedded FLASH integrated circuit comprising:

forming a first photoresist film over a semiconductor substrate;

patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor;

partially etching said first region of said polycrystalline silicon film;

removing said first photoresist film;

forming and patterning a second photoresist film; and

etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.

6. The method of claim 5 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.

7. The method of claim 5 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl₂/CF₄/HeO₂ plasma etch process.

8. A method of simultaneously forming FLASH memory cell gate stacks and NMOS and PMOS gate structures on an embedded integrated circuit comprising:

forming a first photoresist film over a semiconductor substrate;

patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor;

implanting said first region of said polycrystalline silicon film with a n-type dopant species;

partially etching said first region of said polycrystalline silicon film;

removing said first photoresist film;

forming and patterning a second photoresist film; and

etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.

9. The method of claim 8 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.

10. The method of claim 8 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl₂/CF₄/HeO₂ plasma etch process.

11. The method of claim 8 wherein said etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor is a multiple step process, comprising:

a control gate etch comprising a HBr/Cl₂/CF₄/HeO₂ based plasma etch;

a CHF₃/O₂ based plasma interpoly dielectric etch;

a HBr/Cl₂/HeO₂ plasma based gate etch; and

a HBr/HeO₂ based plasma over etch.