Dopant diffusion-retarding barrier region formed within polysilicon gate layer

• US 6,380,055 B2
• Filed: 10/22/1998
• Issued: 04/30/2002
• Est. Priority Date: 10/22/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Wristers, Derick J., Hause, Frederick N., Gardner, Mark I., Fulford, H. Jim Jr., Moore, Bradley T.
• Primary Examiner(s): Ghyka, Alexander G.
• Application Number:
  US09/177,043
• Publication Number:
  US 20020004294A1
• Time in Patent Office: 1,286 Days
• Field of Search: 438/585, 438/592, 438/560
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916

Abstract

A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.

Claims

1. A method of fabricating a gate electrode structure for an insulated gate field effect transistor (IGFET), said method comprising:

forming a polysilicon layer on an underlying gate dielectric layer, said polysilicon layer having top and bottom surfaces, said bottom surface forming an interface with said gate dielectric layer;

implanting a nitrogen-containing material to form a nitrogen-containing diffusion-retarding barrier region within said polysilicon layer;

introducing a dopant into at least a portion of said polysilicon layer disposed between said barrier region and said top surface, said dopant introduction resulting in a greater dopant concentration immediately above said barrier region than immediately below; and

removing regions of said polysilicon layer to form a gate electrode for said IGFET.

2. The method of claim 1 wherein nitrogen residing in said gate dielectric layer just below said interface has a negligible concentration.

3. The method of claim 1 wherein said removing is performed before said introducing.

4. The method of claim 1 wherein said removing is performed before said implanting.

5. The method of claim 1 wherein said implanting comprises:

implanting a material chosen from the group consisting of elemental nitrogen (N) and molecular nitrogen (N₂).

6. The method of claim 1 further comprising:

annealing said implanted nitrogen-containing material after said implanting.

7. The method of claim 1 wherein said dopant comprises boron.

8. The method of claim 1 further comprising:

implanting a nitrogen-containing material to form a second nitrogen-containing diffusion-retarding barrier region above and spaced apart from said nitrogen-containing diffusion-retarding barrier region.

9. A method of fabricating a gate electrode structure for an insulated gate field effect transistor (IGFET), said method comprising:

forming a polysilicon layer on an underlying gate dielectric layer, said polysilicon layer having top and bottom surfaces, said bottom surface forming an interface with said gate dielectric layer;

implanting a nitrogen-containing material to form a nitrogen n-containing diffusion-retarding barrier region within said polysilicon layer, said barrier region separated from both said interface and said top surface;

implanting a boron-containing material into at least a portion of said polysilicon layer between said barrier region and said top surface, resulting in a boron doping profile exhibiting a greater doping concentration immediately above said barrier region than immediately below; and

removing regions of said polysilicon layer to form a gate electrode for said IGFET.

10. The method of claim 9 wherein said removing is performed before said implanting a boron-containing material.

11. The method of claim 9 wherein said removing is performed before said implanting a nitrogen-containing material.

12. The method of claim 9 further comprising:

annealing said implanted nitrogen-containing material after said implanting.