Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components

• US 6,380,555 B1
• Filed: 12/24/1999
• Issued: 04/30/2002
• Est. Priority Date: 12/24/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hembree, David R., de Varona, Jorge L.
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US09/473,232
• Time in Patent Office: 858 Days
• Field of Search: 257/48, 257/673, 257/780, 257/782
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier

Abstract

A bumped semiconductor component includes bumped contacts, a semiconductor die having die contacts, and a redistribution circuit having conductors for establishing electrical communication between the die contacts and the bumped contacts. The redistribution circuit also includes test contacts in electrical communication with the die contacts and with the bumped contacts. The test contacts allow the die to be tested without electrical engagement of the bumped contacts. The bumped semiconductor component can be contained on a wafer, or can be a singulated component such as a flip chip package. A test system includes the bumped semiconductor component, and an interconnect having contacts configured to electrically engage the test contacts without interference from the bumped contacts. If the test contacts are aligned with the die contacts, the same interconnect can be used to test the bare die as well as the bumped component. A test method includes the steps of: providing the bumped component with test contacts; providing the interconnect with interconnect contacts configured to engage the test contacts without interference from the bumped contacts; and then testing the component by applying test signals through the interconnect contacts to the test contacts.

Claims

1. A semiconductor component comprising:

a semiconductor die comprising a plurality of die contacts;

a plurality of redistribution conductors on the die in electrical communication with the die contacts;

a plurality of bumped contacts on the die in electrical communication with the redistribution conductors arranged in an area array;

an electrically insulating layer on the die configured to electrically insulate the redistribution conductors; and

a plurality of test contacts on the die comprising portions of the redistribution conductors and openings in the electrically insulating layer aligned with the portions;

the test contacts configured such that each bumped contact of the area array has an associated test contact which can be physically and electrically contacted by a contact of an interconnect without interference from the bumped contacts for applying test signals to the die.

2. The component of claim 1 wherein the openings and the portions are aligned with the die contacts.

3. The component of claim 1 wherein the bumped contacts are arranged in a grid array and at least some of the test contacts are located in spaces of the grid array.

4. The component of claim 1 wherein the bumped contacts comprises solder balls and the electrically insulating layer comprises a solder mask.

5. A semiconductor component comprising:

a die having a face and a plurality of die contacts on the face;

a plurality of redistribution conductors on the face in electrical communication with the die contacts;

a passivation layer on the die configured to electrically insulate the redistribution conductors;

a plurality of bumped contacts on the passivation layer in electrical communication with the redistribution conductors;

a plurality of test contacts on the die, each bumped contact having an associated test contact, each test contact comprising an opening in the passivation layer aligned with a portion of a conductor and a die contact;

the test contacts configured for electrical engagement by contacts of a test interconnect configured to test the component or the die.

6. The semiconductor component of claim 5 wherein each test contact comprises a conductive material in the opening.

7. The semiconductor component of claim 5 wherein the bumped contacts comprise balls in a ball grid array and each ball of the ball grid array has an associated test contact.

8. The semiconductor component of claim 5 wherein the bumped contacts are arranged in an area array and at least some of the test contacts are located in spaces of the area array.

9. The semiconductor component of claim 5 wherein the component is contained on a wafer, a panel or a leadframe containing a plurality of components.

10. A semiconductor component comprising:

a semiconductor die comprising a face, and a plurality of die contacts on the face;

a plurality of redistribution conductors on the face in electrical communication with the die contacts;

an outer passivation layer on the face and on the redistribution conductors;

a plurality of first openings in the passivation layer in a grid array;

a plurality of bumped contacts in the first openings in the grid array in electrical communication with the redistribution conductors; and

a plurality of test contacts comprising a plurality of second openings in the outer passivation layer and a plurality of pads in the openings in electrical communication with the redistribution conductors, each bumped contact of the grid array having an associated test contact configured to allow electrical access for applying test signals to the component.

11. The semiconductor component of claim 10 wherein the pads comprise a conductive material substantially planar to a surface of the outer passivation layer.

12. The semiconductor component of claim 10 wherein the pads are raised relative to the outer passivation layer.

13. The semiconductor component of claim 10 wherein the bumped contacts comprise solder balls.

14. The semiconductor component of claim 10 wherein the second openings and the test contacts are aligned with the die contacts.

15. The semiconductor component of claim 10 wherein the redistribution conductors have a “

fan out”

configuration, or a “

fan in”

configuration.

16. The semiconductor component of claim 10 wherein the test contacts comprise pads on the second portions of the conductors.

17. A semiconductor component comprising:

a semiconductor die comprising a plurality of die contacts and a die passivation layer;

a redistribution circuit on the die comprising;

a plurality of conductors on the die passivation layer in electrical contact with the die contacts and having first portions and second portions;

an outer passivation layer on the die passivation layer and on the conductors;

a plurality of bumped contacts on the die bonded to the first portions of the conductors and arranged in a grid array; and

a plurality of test contacts comprising a plurality of openings through the outer passivation layer aligned with the second portions of the conductors;

the openings located relative to the bumped contacts such that each bumped contact of the grid array has an associated test contact and the second portions of the conductors can be physically and electrically contacted by a plurality of interconnect contacts.

18. The semiconductor component of claim 17 wherein the component comprises a package.

19. The semiconductor component of claim 17 wherein the bumped contacts comprise solder balls.

20. The semiconductor component of claim 17 wherein the openings and the test contacts are aligned with the die contacts.

21. A system for testing a semiconductor component having a semiconductor die and a plurality of bumped contacts in an area array comprising:

a redistribution circuit on the die comprising a plurality of redistribution conductors in electrical communication with the bumped contacts;

an electrically insulating layer on the die electrically insulating the redistribution conductors;

a plurality of test contacts on the component in electrical communication with the bumped contacts, each bumped contact of the area array having a test contact, each test contact comprising an opening in the electrically insulating layer and a pad in the opening in electrical communication with a redistribution conductor;

an interconnect comprising a plurality of interconnect contacts configured to electrically engage the test contacts without interference from the bumped contacts; and

a testing circuit in electrical communication with the interconnect contacts configured to apply test signals to the component.

22. The system of claim 21 wherein the component comprises a wafer and the system further comprises a wafer prober for moving the wafer towards the interconnect for electrically engaging the test contacts.

23. The system of claim 21 wherein the component comprises a singulated package and the system further comprises a test carrier for temporarily packaging the package.

24. A system for testing a semiconductor wafer having a plurality of bumped contacts in an area array comprising:

a wafer prober;

an interconnect on the wafer prober comprising a plurality of interconnect contacts;

a testing circuit in electrical communication with the interconnect contacts configured to generate test signals; and

a redistribution circuit on the wafer comprising a plurality of conductors in electrical communication with the bumped contacts, an outer passivation layer on the wafer, and a plurality of test contacts comprising openings in the passivation layer aligned with selected portions of the conductors, the test contacts and the bumped contacts configured for electrical engagement by the interconnect contacts, each bumped contact of the area array having an associated test contact.

25. The system of claim 24 wherein the interconnect comprises a probe card.

26. The system of claim 24 wherein the wafer comprises a plurality of die contacts in electrical communication with the bumped contacts and the test contacts are aligned with the die contacts.