DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors

• US 6,380,581 B1
• Filed: 02/26/1999
• Issued: 04/30/2002
• Est. Priority Date: 02/26/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/259,493
• Publication Number:
  US 20020024083A1
• Time in Patent Office: 1,159 Days
• Field of Search: 257/300, 257/316-321, 257/314
• US Class Current: 257/314
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor. The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.

Claims

1. A non volatile memory cell structure, comprising;

a transistor;

a capacitor; and

a vertical electrical via which couples a first plate of the capacitor through an insulator layer to a gate of the transistor, wherein the transistor includes a transistor formed in a semiconductor substrate including a channel and first and a second diffused region in the semiconductor substrate, and wherein a gate for the transistor is separated from the channel by a gate oxide, wherein the capacitor includes a stacked capacitor formed in a subsequent layer above the transistor and separated from the transistor by the insulator layer, wherein the first plate of the stacked capacitor is cup shaped and is separated by a dielectric layer from a second plate of the capacitor.

2. The non volatile memory cell structure of claim 1, wherein the transistor includes an n-channel metal oxide semiconductor (NMOS) transistor.

3. The nonvolatile memory cell structure of claim 1, wherein the transistor includes a transistor formed in a semiconductor substrate including a channel and a first and a second diffused region in the semiconductor substrate, and wherein a gate for the transistor is separated from the channel by a gate oxide.

4. The non volatile memory cell structure of claim 3, wherein the capacitor is separated from the transistor by the insulator layer.

5. A stacked non volatile random access memory (NVRAM), comprising;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and spearated from the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separted by a dielectric layer from a top plate of the capacitor.

6. The NVRAM of claim 5, wherein the electrical contact includes a polysilicon plug.

7. A stacked non volatile random access memory (NVRAM), comprising:

a metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate.

8. A stacked non volatile random access memory (NVRAM), comprising:

a metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the bottom plate serves as a storage node, and wherein the top plate serves as a plate conductor for the stacked capacitor.

9. The NVRAM of claim 8, wherein the NVRAM includes an electrically erasable and programmable read only memory (EEPROM).

10. The NVRAM of claim 8, wherein the NVRAM includes a flash memory cell.

11. An EEPROM cell, comprising:

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, wherein the MOSFET includes a gate separated by a gate oxide from a channel region, and wherein the channel region couples a first diffused region to a second diffused region;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and

an electrical via coupling a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate.

12. The EEPROM cell of claim 11, wherein the gate oxide has a thickness of less than 100 Å

of SiO₂.

13. The EEPROM cell of claim 11, wherein the stacked capacitor includes a top plate separated from the bottom plate of the capacitor by a capacitor dielectric, and wherein the bottom plate of the stacked capacitor comprises a floating gate for the EEPROM cell, and wherein the top plate comprises a control gate for the EEPROM cell.

14. The EEPROM cell of claim 13, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) to a capacitance between the floating gate and the channel region (C2) is greater than 1.0.

15. The EEPROM cell of claim 13, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) to a capacitance between the floating gate and either the first diffused region or the second diffused region (C2) is greater than 1.0.

16. The EEPROM cell of claim 13, wherein the capacitor dielectric has a thickness of less than 100 Å

SiO₂.

17. An EEPROM cell, comprising:

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, wherein the MOSFET includes a gate separated by a gate oxide from a channel region, and wherein the channel region couples a first diffused region to a second diffused region;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and

an electrical via coupling a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET, wherein the stacked capacitor includes a double sided stacked type capacitor structure having at least one roughened surface.

18. A EEPROM cell, comprising:

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, wherein the MOSFET includes a gate separated by a gate oxide from a channel region, and wherein the channel region couples a first diffused region to a second diffused region;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separted from the MOSFET by an insulator layer; and

an electrical via coupling a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET, wherein the stacked capacitor includes a fin type capacitor structure, wherein the fin type capacitor structure includes opposing sides, each of the opposing sides including multiple plates, the multiple plates being separated by a dielectric layer.

19. A non volatile memory array, comprising:

a number of non volatile memory cells wherein each non volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a stacked capacitor having a bottom plate, a capacitor dielectric, and a top plate, wherein the stacked capacitor is formed in a subsequent layer above the MOSFET, and wherein the stacked capacitor is separated from the MOSFET by an insulator layer; and

an electrical contact coupling the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer;

a wordline coupled to the top plate of the stacked capacitor in the number of non volatile memory cells;

a bit line coupled to a drain region of the MOSFET in the number of non volatile memory cells; and

a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls, wherein the capacitor dielectric is conformal to the bottom plate, and wherein the top plate is conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

20. The non volatile memory array of claim 19, wherein the non volatile memory array is formed on a DRAM chip.

21. The non volatile memory array of claim 19, wherein the electrical contact includes a polysilicon plug.

22. The non volatile memory array of claim 19, wherein the gate of the MOSFET serves as a floating gate, and wherein the top plate of the stacked capacitor serves as a control gate in the number of non volatile memory cells.

23. The non volatile memory array of claim 19, wherein the array of non volatile memory cells includes an array of electrically erasable and programmable read only memories (EEPROMs).

24. The non volatile memory array of claim 19, wherein the array of non volatile memory cells includes an array of flash memory cells.

25. An electronic system, comprising:

a processor;

a dynamic random access memory (DRAM) chip; and

a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a non volatile memory array, and wherein the non volatile memory array includes;

a number of non volatile memory cells wherein each non volatile memory cell includes;

a MOSFET formed in a semiconductor substrate;

a stacked capacitor, wherein the stacked capacitor is formed above the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer;

a wordline coupled to a top plate of the stacked capacitor in the number of non volatile memory cells;

a bit line coupled to a drain region of the MOSFET in the number of non volatile memory cells; and

a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate.

26. The electronic system of claim 25, wherein the electrical contact includes a polysilicon plug.

27. The electronic system of claim 25, wherein the MOSFET includes a gate oxide which has a thickness of less than 100 Å

SiO₂.

28. The electronic system of claim 25, wherein the top plate of the stacked capacitor server as a control gate, and wherein a gate for the MOSFET serves as a floating gate for the number of non volatile memory cells.

29. The electronic system of claim 28, wherein a capacitive coupling ratio (C1/C2) of a capacitance between the control gate and the floating gate (C1) of the MOSFET is greater than 1.0 in the number of non volatile memory cells.

30. An electronic system, comprising:

a processor;

a dynamic random access memory (DRAM) chip; and

a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a non volatile memory array, and wherein the non volatile memory array includes;

a number of non volatile memory cells wherein each non volatile memory cell includes;

a MOSFET formed in a semiconductor substrate;

a stacked capacitor, wherein the stacked capacitor is separated from the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET through tie insulator layer;

a wordline coupled to a top plate of the stacked capacitor in the number of non volatile memory cells;

a bit line coupled to a drain region of the MOSFFT in the number of non volatile memory cells; and

a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells, wherein the stacked capacitor includes a double sided stacked type capacitor structure having at least one roughened surface.

31. An electronic system, comprising:

a processor;

a dynamic random access memory (DRAM) chip; and

a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a non volatile memory array, and wherein the non volatile memory array includes;

a number of non volatile memory cells wherein each non volatile memory cell includes;

a MOSFET formed in a semiconductor substrate;

a stacked capacitor, wherein the stacked capacitor is separated from the MOSFET by an insulator layer; and

an electrical contact coupling a bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer;

a wordline coupled to a top plate of the stacked capacitor in the number of non volatile memory cells;

a bit line coupled to a drain region of the MOSFET in the number of non volatile memory cells; and

a sourceline coupled to a source region of the MOSFET in the number of non volatile memory cells, wherein the stacked capacitor includes a fin type capacitor structure ,wherein the fin type capacitor structure includes opposing sides, each of the opposing sides including multiple plates, the multiple plated being separated by a dielectric layer.

32. A method for forming a non volatile memory cell on a DRAM chip, comprising:

forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip;

forming a stacked capacitor above a gate of the MOSFET using a DRAM process, wherein the stacked capacitor is separated by an insulator layer from the MOSFET; and

forming an electrical contact such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer, wherein forming a stacked capacitor includes forming a stacked capacitor having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor, and wherein a portion of the top plate is located within the interior walls of the bottom plate.

33. The method of claim 32, wherein forming an electrical contact includes forming a polysilicon plug.

34. The method of claim 32, wherein forming a MOSFET includes forming an n-channel metal oxide semiconductor (NMOS) transistor.

35. A method for forming a non volatile memory array on a DRAM chip, comprising:

forming a plurality of metal oxide semiconductor field effect transistors (MOSFETs) in a semiconductor substrate on the DRAM chip;

forming a plurality of stacked capacitors in an insulator layer above a gate for each of the plurality of MOSFETs;

electrically coupling a bottom plate for each of the plurality of stacked capacitors to the gates of each of the plurality of the MOSFETs using a contact plug formed according to a DRAM process technology;

coupling a wordline to the top plate for each of the stacked capacitors in the plurality of stacked capacitors;

coupling a bit line to a drain region for each of the MOSFETs in the plurality of MOSFETs; and

coupling a sourceline a source region for each of the MOSFETs in the plurality of MOSFETs, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors each having a cup-shaped bottom plate with interior walls, a capacitor dielectric conformal to the bottom plate, and a top plate conformal to the capacitor, and wherein a portion of the top plate is located within the interior walls of the bottom plate.

36. A method for operating a memory cell, comprising:

controlling a charge placed on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placed on a bottom plate of a stacked capacitor which is formed above the MOSFET and is coupled to the gate by an electrical contact through an insulator; and

wherein controlling the charge placed on the gate and on the bottom plate regulates a threshold voltage (Vt) for the memory cell, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate.

37. The method of claim 36, wherein the method further includes:

applying a potential to the top plate of the stacked capacitor; and

detecting a current flow between a first diffused region and a second diffused region in the MOSFET.

38. A method for operating a memory device, comprising:

placing a charge on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placing a charge on a bottom plate of a stacked capacitor, wherein the stacked capacitor is formed above the MOSFET by an insulator layer, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from a top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate, and wherein an electrical contact couples the bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer;

applying a potential to the top plate of the stacked capacitor; and

detecting a current flow between a first diffused region and a second diffused region in the MOSFET.

39. A method for programming a memory device, comprising:

grounding a source region for a metal oxide semiconductor field effect transistor (MOSFET);

applying a control gate voltage to a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET, wherein the capacitor is formed above the MOSFET, wherein the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, wherein the bottom plate of the staked capacitor is cup shaped having interior walls and is separated by a dielectric layer from the top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate, and wherein the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET;

applying a drain voltage of approximately half the control gate voltage to a drain region of the MOSFET; and

wherein an electrical charge is placed on the gate of the MOSFET and the bottom plate of the stacked capacitor.

40. A method for programming a memory device, comprising:

applying a voltage potential to a source region for a metal oxide semiconductor field effect transistor (MOSFET);

grounding a top plate of a stacked capacitor formed in an insulator layer separating the stacked capacitor from the MOSFET, wherein the capacitor is formed above the MOSFET, wherein the stacked capacitor includes a bottom plate separated by a capacitor dielectric from the top plate, wherein the bottom plate of the stacked capacitor is cup shaped having interior walls and is separated by a dielectric layer from the top plate of the capacitor, wherein the dielectric layer is conformal to the bottom plate, and wherein the top plate is conformal to the dielectric layer, a portion of the top plate being located within the interior walls of the bottom plate, and wherein the bottom plate is electrically coupled by an electrical via through the insulator layer to a gate of the MOSFET;

disconnecting a drain region of the MOSFET from a voltage supply; and

wherein an electrical charge is removed from the gate of the MOSFET and removed from the bottom plate of the stacked capacitor.