Trench-type insulated gate bipolar transistor

• US 6,380,586 B1
• Filed: 02/04/2000
• Issued: 04/30/2002
• Est. Priority Date: 02/05/1999
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Yoshikawa, Koh
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/498,928
• Time in Patent Office: 816 Days
• Field of Search: 257/132, 257/133, 257/137, 257/329, 257/330, 257/331, 257/332, 257/378, 257/565, 257/587
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench-type IGBT is disclosed that facilitates reducing the tradeoff relation between the saturation voltage and the turn-off loss. The trench-type IGBT'"'"'s includes the following characteristic structures: (1) the drift layer of the first conductivity type has extended portions extended between the selectively formed well regions of the second conductivity type; (2) the well regions of the second conductivity type are formed selectively in the respective surface portions of the drift layer of the first conductivity type, and the doped regions of the first conductivity type, doped more heavily than the drift layer, are formed in the other surface portions of the drift layer, wherein the well regions are not formed; (3) the auxiliary gate electrode is disposed above the extended portion of the drift layer of the first conductivity type extended between p-type well regions or above the doped region of the first conductivity type with the auxiliary gate insulation film interposed therebetween; (4) the trenches include respective portions not surrounded by any well region of the second conductivity type nor by any emitter region of the first conductivity type; and (5) the ratio W_t/W_p of the width W_t of the trench and the width W_p of the p-type well region is set at a value between 1 and 20.

Claims

1. A trench-type insulated gate bipolar transistor comprising:

a drift layer of a first conductivity type;

well regions of a second conductivity type in the surface portion of the drift layer;

emitter regions of the first conductivity type in the respective well regions;

trenches extending from the emitter regions to the drift layer;

gate electrodes, each thereof being buried in each of the trenches with a gate insulation film interposed therebetween;

an emitter electrode in common contact with the emitter regions and the well regions;

a collector layer of the second conductivity type on the back surface of the drift layer;

a collector electrode located on the collector layer;

wherein the well regions are formed selectively; and

wherein the drift layer includes extended portions that extend between the well regions.

2. The trench-type insulated gate bipolar transistor according to claim 1, further comprising auxiliary gate insulation films on the respective extended portions of the drift layer and auxiliary gate electrodes on the respective auxiliary gate insulation films.

3. The trench-type insulated gate bipolar transistor according to claim 2 wherein the gate electrodes are connected to the respective auxiliary gate electrodes.

4. The trench-type insulated gate bipolar transistor according to claim 1, wherein the trenches comprise respective portions not surrounded by any of the well regions nor by any of the emitter regions.

5. The trench-type insulated gate bipolar transistor according to claim 4, wherein the trenches are shaped with respective stripes, and the well regions are shaped with respective stripes extending in perpendicular to the stripes of the trenches.

6. The trench-type insulated gate bipolar transistor according to claim 5, wherein the stripe of the well region is divided into rectangles spaced apart from each other by the stripes of the trenches.

7. The trench-type insulated gate bipolar transistor according to claim 6, wherein the emitter regions are shaped with respective rectangles extending in parallel to the stripes of the trenches.

8. The trench-type insulated gate bipolar transistor according to claim 6, wherein the emitter regions are shaped with respective rectangles extending in perpendicular to the stripes of the trenches.

9. The trench-type insulated gate bipolar transistor according to claim 5, wherein the stripe of the trench is divided into rectangles terminated by the well regions, and the emitter regions are arranged along the short sides of the rectangular trenches.

10. A trench-type insulated gate bipolar transistor comprising:

a drift layer of a first conductivity type;

well regions of a second conductivity type in the surface portion of the drift layer;

emitter regions of the first conductivity type in the respective well regions;

trenches extending from the emitter regions to the drift layer;

gate electrodes, each thereof being buried in each of the trenches with a gate insulation film interposed therebetween;

an emitter electrode in common contact with the emitter regions and the well regions;

a collector layer of the second conductivity type on the back surface of the drift layer;

a collector electrode on the collector layer;

wherein the well regions are formed selectively; and

wherein the doped regions of the first conductivity type in the respective surface portions of the drift layer, where the well regions are not formed, the doped regions being doped more heavily than the drift layer.

11. The trench-type insulated gate bipolar transistor according to claim 10, wherein the surface impurity concentration of the doped regions is 1×

10¹⁶ cm<sup>−

3</sup> or less.

12. A The trench-type insulated gate bipolar transistor according to claim 11, further comprising auxiliary gate insulation films on the respective doped regions and auxiliary gate electrodes on the respective auxiliary gate insulation films.

13. The trench-type insulated gate bipolar transistor according to claim 10, further comprising auxiliary gate insulation films on the respective doped regions and auxiliary gate electrodes on the respective auxiliary gate insulation films.

14. The trench-type insulated gate bipolar transistor according to claim 13 wherein the gate electrodes are connected to the respective auxiliary gate electrodes.

15. The trench-type insulated gate bipolar transistor according to claim 10, wherein the trenches comprise respective portions not surrounded by any of the well regions nor by any of the emitter regions.

16. The trench-type insulated gate bipolar transistor according to claim 15, wherein the trenches are shaped with respective stripes, and the well regions are shaped with respective stripes extending in perpendicular to the stripes of the trenches.

17. The trench-type insulated gate bipolar transistor according to claim 16, wherein the stripe of the well region is divided into rectangles spaced apart from each other by the stripes of the trenches.

18. The trench-type insulated gate bipolar transistor according to claim 17, wherein the emitter regions are shaped with respective rectangles extending in parallel to the stripes of the trenches.

19. The trench-type insulated gate bipolar transistor according to claim 17, wherein the emitter regions are shaped with respective rectangles extending in perpendicular to the stripes of the trenches.

20. The trench-type insulated gate bipolar transistor according to claim 16, wherein the stripe of the trench is divided into rectangles terminated by the well regions, and the emitter regions are arranged along the short sides of the rectangular trenches.

21. A trench-type insulated gate bipolar transistor comprising:

a drift layer of a first conductivity type;

well regions of a second conductivity type in the surface portion of the drift layer;

emitter regions of the first conductivity type in the respective well regions;

trenches extending from the emitter regions to the drift layer;

gate electrodes, each thereof being buried in each of the trenches with a gate insulation film interposed therebetween;

an emitter electrode in common contact with the emitter regions and the well regions;

a collector layer of the second conductivity type on the back surface of the drift layer;

a collector electrode on the collector layer; and

wherein the ratio W_t/W_p of the bottom width W_t of the trench and the width W_p of the well region between the trenches being set at a value between 1 and 20.