Nonvolatile semiconductor memory device having an array structure suitable to high-density integrationization

• US 6,380,636 B1
• Filed: 01/19/2000
• Issued: 04/30/2002
• Est. Priority Date: 07/14/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tamada, Satoru, Kunori, Yuichi, Tatsukawa, Satoshi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Luu, Chuong A.
• Application Number:
  US09/487,177
• Time in Patent Office: 832 Days
• Field of Search: 257/910, 257/390, 257/658, 365/230.03, 365/185.11, 365/185.03, 365/185.13, 365/185.17, 365/185.18, 365/185.09, 365/185.29
• US Class Current: 257/390
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

In a memory cell array having sub-bit lines and sub-source lines formed of a diffusion layer, a main bit line is arranged commonly to the sub-bit lines arranged in multiple columns. A memory cell area can be reduced without restrictions by pitch conditions of the main bit lines.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of nonvolatile memory cells arranged in rows and columns, said plurality of nonvolatile memory cells being divided along a row direction into a plurality of groups each including at least two columns of the memory cells, and being divided along a column direction into a plurality of blocks;

a plurality of sub-bit lines arranged corresponding to the memory cell columns in the blocks, respectively, said plurality of sub-bit lines each connected to the nonvolatile memory cells in a corresponding column in a corresponding block, and each of said plurality of sub-bit lines formed of a first impurity layer at a surface of a semiconductor substrate;

a plurality of sub-source lines formed of second impurity layers at the surface of said semiconductor substrate and provided corresponding to the memory cell columns in the groups in each of the blocks, each sub-source line acting as sources of the nonvolatile memory cells in a column in a corresponding group of a corresponding block;

a plurality of main bit lines each provided corresponding to the group of the nonvolatile memory cells and commonly to the sub-bit lines of each of the blocks of a corresponding group;

a plurality of drain block select gates each provided corresponding to the sub-bit line for connecting a corresponding sub-bit line to a corresponding main bit line when made conductive;

a plurality of main source lines each provided corresponding to the block and commonly to the sub-source lines of a corresponding block; and

source block select gates each provided corresponding to the sub-source line for connecting a corresponding sub-source line to a corresponding main source line when made conductive.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

said drain block select gate includes at least:

a drain block select transistor responsive to a first drain block select signal specifying a memory cell column and a block in a group, and

a drain dummy transistor connected in series to said drain block select transistor, and turned on in response to a second source block select signal specifying a memory cell column and a block of a group; and

said source block select gate includes at least;

a source select transistor turned on in response to a first source block select signal specifying a memory cell column and a block in a group, and

a source dummy transistor turned on in response to a second drain block select signal specifying a memory cell column and a block in a group, said source dummy transistor having a first conduction node connected to said source select transistor and a second conduction node in an open state.

3. The nonvolatile semiconductor memory device according to claim 2, wherein

the main source line is connected to said source select transistor and said first conduction node of said source dummy transistor.

4. The nonvolatile semiconductor memory device according to claim 2, wherein

the main source lines are arranged corresponding to the memory cell columns in each of said groups, respectively.

5. The nonvolatile semiconductor memory device according to claim 1, wherein

a memory unit defined by the group and the block includes two sub-bit lines, and the drain block select gates and the source block select gates arranged on said two sub-bit lines are arranged to couple corresponding sub-bit lines to opposing nodes of a corresponding main bit line.

6. The nonvolatile semiconductor memory device according to claim 1, wherein

the drain block select gate includes a drain block select transistor turned on to electrically connect a corresponding sub-bit line to a corresponding main bit line in response to a drain block select signal specifying a block and a group;

and

the source block select gate includes a source select transistor turned on in response to a source block select signal specifying a block and a group, to electrically connect a corresponding sub-source line to the main source line, said main source line arranged commonly to the sub-source lines of the memory cells of a common block.

7. The nonvolatile semiconductor memory device according to claim 6, wherein

said drain block select gate further includes a drain dummy transistor connected in series to said drain block select transistor, having a gate receiving a drain block select signal specifying another column in a common group and maintaining a conductive state independently of a level of the received drain block select signal;

and

said source block select gate includes a source dummy transistor connected in series to said source select transistor, having a gate receiving a source block select signal specifying another column in a common group and maintaining a conductive state independently of a level of the received source block select signal.

8. The nonvolatile semiconductor memory device according to claim 7, wherein

a memory unit defined by the block and the group includes first and second sub-bit lines, and

said drain dummy transistor and said source dummy transistor are arranged for one of said first and second sub-bit lines.

9. The nonvolatile semiconductor memory device according to claim 7, wherein

a memory unit defined by the block and the group includes first and second sub-bit lines,

the drain block select transistors for said first and second sub-bit lines are arranged at ends on a same side of said first and second sub-bit lines, and

the source block select gates for said first and second sub-bit lines are arranged at ends on a same side of said first and second sub-bit lines, and are opposed to said drain block select transistors.

10. The nonvolatile semiconductor memory device according to claim 7, wherein

said source dummy transistor and said drain dummy transistor are formed of depletion type insulated gate field effect transistors, respectively.

11. The nonvolatile semiconductor memory device according to claim 7, wherein

each of said drain dummy transistors and said source dummy transistors has a drain and a source electrically short-circuited by a low resistance conductor.

12. The nonvolatile semiconductor memory device according to claim 6, wherein

the source block select gates in a memory unit defined by a block and a group in the data read mode are all turned on by said source block select signal, and the sub-source lines are electrically connected to the corresponding main source line.

13. The nonvolatile semiconductor memory device according to claim 1, further comprising:

means for, in the data programming mode, turning on the source select gate of an unselected sub-bit line and apply a program inhibiting voltage to a corresponding sub-source line when the drain select gate for a selected sub-bit line is conductive in a memory unit defined by the block and the group.

14. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cells on different columns in a memory unit defined by the group and the block store data of different sectors, respectively, and a word line corresponding to one memory cell row stores data of a plurality of sectors.

15. The nonvolatile semiconductor memory device according to claim 1, wherein

a memory unit defined by one block and one group includes first and second sub-bit lines connected the memory cells on different columns,

the drain block select gate for the memory unit includes a first drain block select transistor for connecting a first sub-bit line to a corresponding main bit line in response to a first drain block select signal, a second drain block select transistor for connecting a second sub-bit line to the corresponding main bit line in response to a second drain block select signal, and a dummy drain select transistor connected in series to said second drain block select transistor and made normally conductive and having a control gate receiving the first drain block select signal, and

the source block select gate for the memory unit includes a first source select transistor for connecting the first sub-bit line to a corresponding source line in response to a first source block select signal, a second source select transistor for connecting the second sub-bit line to the corresponding source line in response to a second source block select signal, and a source dummy transistor connected in series to said second source select transistor and having a control gate receiving said first source block select signal and made normally conductive.

16. The nonvolatile semiconductor memory device according to claim 15, wherein the first and second drain block select signals are different select signals, and the first and second source block select signals are different select signals.

17. The nonvolatile semiconductor memory device according to claim 15, wherein the first and second drain block select signals are a common select signal, and the first and second source block select signals are a common select signal.

18. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cells arranged alignedly in the row direction are formed on separated substrate regions on a semiconductor substrate, respectively.