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Nonvolatile semiconductor memory device having an array structure suitable to high-density integrationization

  • US 6,380,636 B1
  • Filed: 01/19/2000
  • Issued: 04/30/2002
  • Est. Priority Date: 07/14/1999
  • Status: Expired due to Term
First Claim
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1. A nonvolatile semiconductor memory device comprising:

  • a plurality of nonvolatile memory cells arranged in rows and columns, said plurality of nonvolatile memory cells being divided along a row direction into a plurality of groups each including at least two columns of the memory cells, and being divided along a column direction into a plurality of blocks;

    a plurality of sub-bit lines arranged corresponding to the memory cell columns in the blocks, respectively, said plurality of sub-bit lines each connected to the nonvolatile memory cells in a corresponding column in a corresponding block, and each of said plurality of sub-bit lines formed of a first impurity layer at a surface of a semiconductor substrate;

    a plurality of sub-source lines formed of second impurity layers at the surface of said semiconductor substrate and provided corresponding to the memory cell columns in the groups in each of the blocks, each sub-source line acting as sources of the nonvolatile memory cells in a column in a corresponding group of a corresponding block;

    a plurality of main bit lines each provided corresponding to the group of the nonvolatile memory cells and commonly to the sub-bit lines of each of the blocks of a corresponding group;

    a plurality of drain block select gates each provided corresponding to the sub-bit line for connecting a corresponding sub-bit line to a corresponding main bit line when made conductive;

    a plurality of main source lines each provided corresponding to the block and commonly to the sub-source lines of a corresponding block; and

    source block select gates each provided corresponding to the sub-source line for connecting a corresponding sub-source line to a corresponding main source line when made conductive.

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