Digital PLL filter and VCO for use in controlling a spindle motor of a mass data storage device

• US 6,380,703 B1
• Filed: 03/15/2001
• Issued: 04/30/2002
• Est. Priority Date: 03/15/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: White, Bertram J.
• Primary Examiner(s): Nappi, Robert E.
• Assistant Examiner(s): Duda, Rina I.
• Application Number:
  US09/681,308
• Time in Patent Office: 411 Days
• Field of Search: 388/254, 388/138, 388/439, 388/459, 388/500, 388/928.1
• US Class Current: 318/400.13
• CPC Class Codes: G11B 19/28 Speed controlling, regulating, or indicating G11B19/24 takes precedence
• CPC Class Codes: H02P 23/186 of one shaft by controlling the prime mover
• CPC Class Codes: H02P 6/08 Arrangements for controlling the speed or torque of a single motor H02P6/10, H02P6/28 take precedence
• CPC Class Codes: H02P 6/14 Electronic commutators

Abstract

A circuit for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device includes an accumulator (48) to accumulate a digital count that is proportional or related to a phase difference between the commutation control signals and a motor bemf. A digital variable frequency oscillator (52) generates an oscillator output signal of frequency proportional to the digital count to reset the accumulator (68) after a predetermined time determined by the frequency. The circuit may also include a digital filter (50) between the digital accumulator (48) and the digital variable frequency oscillator (52) to generate a magnitude signal (DRC) of magnitude proportional to the accumulated count for delivery to the variable frequency oscillator (52) to control the frequency thereof.

Claims

1. A circuit for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device, comprising:

an accumulator to accumulate a digital count that is related to a phase difference between said commutation control signals and a motor bemf; and

a digital variable frequency oscillator to generate an oscillator output signal of frequency related to said digital count to reset said accumulator after a predetermined time determined by said frequency.

2. The circuit of claim 1 further comprising a digital filter between said digital accumulator and said digital variable frequency oscillator to generate a magnitude signal of magnitude related to said count for delivery to said variable frequency oscillator to control the frequency thereof.

3. The circuit of claim 2 wherein said output signal of said variable frequency oscillator is a sign of a signal generated by said variable frequency oscillator.

4. The circuit of claim 3 wherein said variable frequency oscillator is an accumulator that accumulates a count related to said magnitude signal.

5. The circuit of claim 1 further comprising a first feedback circuit to feedback an accumulated digital count signal to said accumulator to additively increase a count in said accumulator in dependence upon said accumulated digital count.

6. The circuit of claim 5 further comprising an inverter circuit to control a sign of accumulated digital count signal fed back to said accumulator in accordance with a direction of said phase difference between said commutation control signals and a motor bemf.

7. The circuit of claim 2 further comprising circuits for weighting said digital count and said magnitude signal.

8. The circuit of claim 7 wherein at least one of said circuits for weighting said digital count and said magnitude signal is user programmable.

9. A circuit for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device, comprising:

means for accumulating a digital count that is related to a phase difference between said commutation control signals and a motor bemf; and

means for generating an oscillator output signal of frequency related to said phase difference to reset said means for accumulating after a predetermined time determined by said frequency.

10. The circuit of claim 9 further comprising means for digitally filtering the accumulated digital count to generate a magnitude signal of magnitude related to said count for delivery to said means for generating an oscillator output signal to control the frequency thereof.

11. The circuit of claim 10 wherein said output signal of said means for generating an oscillator output signal is a sign of a signal generated by said means for generating an oscillator output signal.

12. The circuit of claim 10 wherein said means for generating an oscillator output signal comprises means for accumulating a count related to said magnitude signal.

13. A method for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device, comprising:

accumulating a digital count that is related to a phase difference between said commutation control signals and a motor bemf; and

generating an oscillator output signal of frequency related to said digital count to reset said accumulator after a predetermined time determined by said frequency.

14. A method for controlling a commutation timing of a polyphase dc motor comprising:

accumulating a digital count representing a difference between a bemf voltage of said motor and a reference signal;

using said accumulated digital count to generate a digital feedback word for accumulation during a subsequent accumulation window with a previously accumulated value; and

using said accumulated digital count to also control a frequency of a periodically reoccurring reference signal to provide said reference signal, to determine said accumulation window, and to control said commutation timing.

15. The method of claim 14 further comprising weighting said accumulated value in accordance with a number of pulse-width-modulated cycles existing in said accumulation window.

16. The method of claim 14 further comprising integrating said accumulated value to produce said digital feedback word.

17. A method for controlling a commutation timing of a polyphase dc motor comprising:

determining if a phase detection window has begun;

if a phase detection window has begun, loading a register with a first increment value;

determining if the phase detection window has ended;

if the phase detection window has not ended, continuing to add an increment value to an accumulation register;

if the phase detection window has ended, integrating a value in the accumulation register in an integrating accumulator;

and storing the integrated value in a register, said integrated value establishing a reference frequency and establishing when said phase detection window has begun and ended.

18. The method of claim 17 further comprising weighting said accumulated value in accordance with a number of pulse-width-modulated cycles existing in said accumulation window.

19. A mass data storage device, comprising:

a circuit for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device, said circuit including;

an accumulator to accumulate a digital count that is related to a phase difference between said commutation control signals and a motor bemf; and

a digital variable frequency oscillator to generate an oscillator output signal of frequency related to said digital count to reset said accumulator after a predetermined time determined by said frequency.

20. The mass data storage device of claim 19 further comprising a digital filter between said digital accumulator and said digital variable frequency oscillator to generate a magnitude signal of magnitude related to said count for delivery to said variable frequency oscillator to control the frequency thereof.

21. The mass data storage device of claim 20 wherein said output signal of said variable frequency oscillator is a sign of a signal generated by said variable frequency oscillator.

22. The mass data storage device of claim 21 wherein said variable frequency oscillator is an accumulator that accumulates a count related to said magnitude signal.

23. The mass data storage device of claim 19 further comprising a first feedback circuit to feedback an accumulated digital count signal to said accumulator to additively increase a count in said accumulator in dependence upon said accumulated digital count.

24. The mass data storage device of claim 23 further comprising an inverter circuit to control a sign of accumulated digital count signal fed back to said accumulator in accordance with a direction of said phase difference between said commutation control signals and a motor bemf.

25. The mass data storage device of claim 20 further comprising circuits for weighting said digital count and said magnitude signal.

26. The mass data storage device of claim 25 wherein at least one of said circuits for weighting said digital count and said magnitude signal are user programmable.