Testing integrated circuit dice

• US 6,380,729 B1
• Filed: 02/16/1999
• Issued: 04/30/2002
• Est. Priority Date: 02/16/1999
• Status: Expired due to Term

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: Alien Technology Corporation
• Inventors: Smith, John Stephen
• Primary Examiner(s): Brown, Glenn W.
• Application Number:
  US09/251,269
• Time in Patent Office: 1,169 Days
• Field of Search: 324/765, 324/763, 324/158.1, 257/209, 257/48, 257/767, 437/8, 438/17, 438/18, 438/19
• US Class Current: 324/759.02
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]

Abstract

A method for testing a plurality of integrated circuits. In one embodiment, a plurality of integrated circuits are arranged on a wafer. The integrated circuits are separated on the wafer across the boundary region. Testing interconnects are disposed across the boundary region to test switchable couplings included in each of the integrated circuits on the wafer. After the integrated circuits are tested on the wafer using the testing interconnects across the boundary region, the boundary region is removed, which separates the wafer into individual integrated circuit dice and severs the testing interconnects.

Claims

1. A method for testing a plurality of integrated circuits, the method comprising:

arranging the plurality of integrated circuits on a wafer, the plurality of the integrated circuits including a first integrated circuit arranged on the wafer adjacent to a second integrated circuit;

coupling across a boundary region of the wafer a first end of a switchable coupling of the first integrated circuit to a first end of a switchable coupling of the second integrated circuit;

verifying a switchable coupling between a second end of the switchable coupling of the first integrated circuit and a second end of the switchable coupling of the second integrated circuit across the boundary region of the wafer; and

removing the boundary region of the wafer to separate the first integrated circuit from the second integrated circuit.

2. The method of claim 1 wherein removing the boundary region of the wafer includes severing a testing interconnect coupling across the boundary region of the wafer the first end of the switchable coupling of the first integrated circuit to the first end of the switchable coupling of the second integrated circuit.

3. The method of claim 1 wherein verifying the switchable coupling between the second end of the switchable coupling of the first integrated circuit and the second end of the switchable coupling of the second integrated circuit comprises:

selecting the first end of the switchable coupling of the first integrated circuit to be coupled to the second end of the switchable coupling of the first integrated circuit;

selecting the first end of the switchable coupling of the second integrated circuit to be coupled to the second end of the switchable coupling of the second integrated circuit; and

verifying that the second end of the switchable coupling of the first integrated circuit is coupled to the second and of the switchable coupling of the second integrated circuit.

4. The method of claim 1 wherein verifying the switchable coupling between the second end of the switchable coupling of the first integrated circuit and the second end of the switchable coupling of the second integrated circuit comprises:

selecting the first end of the switchable coupling of the first integrated circuit to be decoupled from the second end of the switchable coupling of the first integrated circuit;

selecting the first end of the switchable coupling of the second integrated circuit to be decoupled from the second end of the switchable coupling of the second integrated circuit; and

verifying that the second end of the switchable coupling of the first integrated circuit is decoupled from the second and of the switchable coupling of the second integrated circuit.

5. The method of claim 1 further including marking the first and second integrated circuits if the verifying is unsuccessful.

6. The method of claim 1 further including marking the first and second integrated circuits if the verifying is successful.

7. The method of claim 1 wherein the plurality of integrated circuits further includes a third integrated circuit arranged on the wafer adjacent to a fourth integrated circuit, the method further including:

coupling across the boundary region of the wafer a first end of a switchable coupling of the third integrated circuit to a first end of a switchable coupling of the fourth integrated circuit;

verifying a switchable coupling between a second end of the switchable coupling of the third integrated circuit and a second end of the switchable coupling of the fourth integrated circuit across the boundary region of the wafer; and

separating at the boundary region of the wafer the third integrated circuit from the fourth integrated circuit.

8. A wafer including a plurality of integrated circuit dice arranged in an array, comprising:

a first switchable coupling included in a first integrated circuit die included among the plurality of integrated circuit dice;

a second switchable coupling included in a second integrated circuit die included among the plurality of integrated circuit dice, the first integrated circuit die arranged in the array adjacent to the second integrated circuit die across a boundary region, the boundary region to be removed from the wafer to separate the plurality of the integrated circuit dice; and

a testing interconnect coupled between a first end of the first switchable coupling and a first end of the second switchable coupling across the boundary region such that a second end of the first switchable coupling is switchably coupled to a second end of the second switchable coupling.

9. The wafer of claim 8, further comprising a first select line coupled to the first and second switchable couplings across the boundary region to selectively activate or deactivate the first and second switchable couplings.

10. The wafer of claim 9, further comprising:

a second select line coupled to the first switchable coupling across the boundary region; and

a third select line coupled to the second switchable coupling across the boundary region, the second and third select lines to selectively activate or deactivate the first and second switchable couplings, respectively.

11. The wafer of claim 9, further comprising:

a third switchable coupling included in the first integrated circuit die, the third switchable coupling having a second end coupled to the second end of the to first switchable coupling; and

a fourth select line coupled to the third switchable coupling across the boundary region to selectively activate or deactivate the third switchable coupling, the third switchable coupling to be deactivated when the first switchable coupling is activated.

12. The wafer of claim 11, further comprising:

a fourth switchable coupling included in the second integrated circuit die, the fourth switchable coupling having a second and coupled to the second end of the second switchable coupling; and

a fifth select line coupled to the fourth switchable coupling across the boundary region to selectively activate or deactivate the fourth switchable coupling, the fourth switchable coupling to be deactivated when the second switchable coupling is activated.

13. The wafer of claim 11, further comprising:

a fourth switchable coupling included in the second integrated circuit die, the fourth switchable coupling having a second and coupled to the second end of the second switchable coupling;

the fourth select line coupled to the fourth switchable coupling across the boundary region to selectively activate or deactivate the fourth switchable coupling, the fourth switchable coupling to be deactivated when the second switchable coupling is activated.

14. The wafer of claim 8, further comprising:

a fifth switchable coupling included in a third integrated circuit die included among the plurality of integrated circuit dice; and

a second testing interconnect coupled between the second end of the first switchable coupling and a second end of the fifth switchable coupling across the boundary region.

15. The wafer of claim 14, further comprising:

a sixth switchable coupling included in a fourth integrated circuit die included among the plurality of integrated circuit dice;

a third testing interconnect coupled between the second of the second switchable coupling and a second end of the sixth switchable coupling across the boundary region.

16. A method for testing a plurality of integrated circuits, the method comprising:

providing a wafer having the plurality of integrated circuits arranged thereon, the wafer including a boundary region disposed between each one of the plurality of integrated circuits;

coupling an output of the a first switchable coupling of a first one of the plurality of integrated circuits to an output of a second switchable coupling of second one of the plurality of integrated circuits, the output of the first and second switchable couplings coupled through a first testing interconnect disposed across the boundary region;

activating selectively through a second testing interconnect disposed across the boundary region the first and second switchable couplings;

accessing through a third testing interconnect disposed across the boundary region an input of the first switchable coupling;

accessing through a fourth testing interconnect disposed across the boundary region an input of the second switchable coupling;

verifying a switchable coupling between the first and second switchable couplings through the third and fourth testing interconnects; and

removing the boundary region of the wafer to separate the plurality of integrated circuits.

17. The method of claim 16 wherein removing the boundary region of the wafer includes severing the first, second, third and the fourth testing interconnects.

18. The method of claim 16 further including deactivating selectively through a fifth testing interconnect disposed across the boundary region a third switchable coupling.

19. The method of claim 16 wherein verifying the switchable coupling between the first and second switchable couplings includes identifying a short circuit in the first and second switchable couplings.

20. The method of claim 16 wherein verifying the switchable coupling between the first and second switchable couplings includes identifying and open circuit in the first and second switchable couplings.

21. The method of claim 16 wherein verifying the switchable coupling between the first and second switchable couplings includes identifying the failed transistor of the first and second switchable couplings.

22. The method of claim 16 further including:

deactivating selectively the first and second switchable couplings;

activating selectively through a fifth testing interconnect disposed across the boundary region a third and a fourth switchable coupling;

accessing through the third testing interconnect an input of the third switchable coupling;

accessing through the fourth testing interconnect an input of the fourth switchable coupling; and

verifying a switchable coupling between the third and fourth switchable couplings through the third and fourth switching interconnects.

23. The method of claim 22 further including deactivating selectively through the second testing interconnect the first and second switchable couplings.

24. A method for testing a plurality of integrated circuits, the method comprising arranging the plurality of integrated circuits on a wafer, the plurality of the integrated circuits including a first integrated circuit arranged on the wafer adjacent to a second integrated circuit;

coupling across a boundary region of the wafer the first integrated circuit to the second integrated circuit;

verifying a switchable coupling between a second end of the switchable coupling of the first integrated circuit and a second end of the switchable coupling of the second integrated circuit across the boundary region of the wafer; and

removing the boundary region of the wafer to separate the first integrated circuit from the second integrated circuit.

25. The method of claim 24 wherein coupling across the boundary region of the wafer the first integrated circuit to the second integrated circuit includes coupling a first end of a switchable coupling of the first integrated circuit to a first end of a switchable coupling of the second integrated circuit.

26. The method of claim 25 wherein verifying the first integrated circuit with the second integrated circuit across the boundary region of the wafer includes verifying a switchable coupling between a second end of the switchable coupling of the first integrated circuit and a second end of the switchable coupling of the second integrated circuit across the boundary region of the wafer.

27. The method of claim 24 wherein removing the boundary region of the wafer includes severing a testing interconnect coupling across the boundary region of the wafer the first integrated circuit to the second integrated circuit.

28. The method of claim 26 wherein verifying the switchable coupling between the second end of the switchable coupling of the first integrated circuit and the second end of the switchable coupling of the second integrated circuit comprises:

selecting the first end of the switchable coupling of the first integrated circuit to be coupled to the second end of the switchable coupling of the first integrated circuit;

selecting the first end of the switchable coupling of the second integrated circuit to be coupled to the second end of the switchable coupling of the second integrated circuit; and

verifying that the second end of the switchable coupling of the first integrated circuit is coupled to the second and of the switchable coupling of the second integrated circuit.

29. The method of claim 26 wherein verifying the switchable coupling between the second end of the switchable coupling of the first integrated circuit and the second end of the switchable coupling of the second integrated circuit comprises:

selecting the first end of the switchable coupling of the first integrated circuit to be decoupled from the second end of the switchable coupling of the first integrated circuit;

selecting the first end of the switchable coupling of the second integrated circuit to be decoupled from the second end of the switchable coupling of the second integrated circuit; and

verifying that the second end of the switchable coupling of the first integrated circuit is decoupled from the second and of the switchable coupling of the second integrated circuit.

30. The method of claim 24 further including marking the first integrated circuit according to the result of the verification.